仅对英特尔可见 — GUID: sam1403480606329
Ixiasoft
5.1. Cyclone® V器件中每个封装的I/O资源
5.2. Cyclone® V器件的I/O纵向移植
5.3. Cyclone® V器件中的I/O标准支持
5.4. Cyclone® V器件的I/O设计指南
5.5. Cyclone® V器件中I/O Bank的位置
5.6. Cyclone® V器件中的I/O Bank组
5.7. Cyclone® V器件中的I/O单元结构
5.8. Cyclone® V器件中的可编程IOE特性
5.9. Cyclone® V器件中的片上I/O匹配
5.10. Cyclone® V器件的外部I/O匹配
5.11. 专用高速电路
5.12. Cyclone® V器件中的差分发送器
5.13. Cyclone® V器件中的差分接收器
5.14. 源同步时序预算
5.15. Cyclone® V器件中的I/O特性修订历史
仅对英特尔可见 — GUID: sam1403480606329
Ixiasoft
4.1.5.5. GCLK和RCLK网络的时钟输入管脚连接
时钟资源 | CLK (p/n管脚) |
---|---|
GCLK[0,1,2,3,4,5,6,7] | CLK[0,1,2,3] |
GCLK[8,9,10,11] | CLK[4,5,6,7] 2 |
GCLK[0,1,2,3,12,13,14,15] | CLK[8,9,10,11] |
时钟资源 | CLK (p/n管脚) |
---|---|
GCLK[0,1,2,3,4,5,6,7] | CLK[0,1,2,3] |
GCLK[8,9,10,11] | CLK[4,5] 3 |
GCLK[0,1,2,3,12,13,14,15] | CLK[6,7] |
时钟资源 | CLK (p/n管脚) |
---|---|
RCLK[20,24,28,30,34,38,58,59,60,61,62,63,64,68,82,86] | CLK[0] |
RCLK[21,25,29,31,35,39,58,59,60,61,62,63,65,69,83,87] | CLK[1] |
RCLK[22,26,32,36,52,53,54,55,56,57,58,59,60,61,62,63,66,84] | CLK[2] |
RCLK[23,27,33,37,52,53,54,55,56,57,58,59,60,61,62,63,67,85] | CLK[3] |
RCLK[46,47,48,49,50,51,70,74,76,80] | CLK[4] 4 |
RCLK[46,47,48,49,50,51,71,75,77,81] | CLK[5] 4 |
RCLK[52,53,54,55,56,57,72,78] | CLK[6] |
RCLK[52,53,54,55,56,57,73,79] | CLK[7] 4 |
RCLK[0,4,8,10,14,18,40,41,42,43,44,45,64,68,82,86] | CLK[8] |
RCLK[1,5,9,11,15,19,40,41,42,43,44,45,65,69,83,87] | CLK[9] |
RCLK[2,6,12,16,40,41,42,43,44,45,46,47,48,49,50,51,66,84] | CLK[10] |
RCLK[3,7,13,17,40,41,42,43,44,45,46,47,48,49,50,51,67,85] | CLK[11] |
时钟资源 | CLK (p/n管脚) |
---|---|
RCLK[20,24,28,30,34,38,58,59,60,61,62,63,64,68,82,86] | AGF 0 |
RCLK[21,25,29,31,35,39,58,59,60,61,62,63,65,69,83,87] | CLK[1] |
RCLK[22,26,32,36,52,53,54,55,56,57,58,59,60,61,62,63,66,84] | CLK[2] |
RCLK[23,27,33,37,52,53,54,55,56,57,58,59,60,61,62,63,67,85] | CLK[3] |
RCLK[52,53,54,55,56,57,78] | CLK[4] 3 |
RCLK[52,53,54,55,56,57,79] | CLK[5] 3 |
RCLK[0,4,8,40,41,42,43,44,45,64,68,82,86] | CLK[6] |
RCLK[1,5,9,40,41,42,43,44,45,65,69,83,87] | CLK[7] |