仅对英特尔可见 — GUID: jbd1486507184657
Ixiasoft
2.2.1. 选择和实例化PHY IP Core
2.2.2. PHY IP Core的配置
2.2.3. 生成PHY IP Core
2.2.4. PLL IP Core的选择
2.2.5. 配置PLL IP Core
2.2.6. PLL IP Core的生成
2.2.7. 复位控制器(Reset Controller)
2.2.8. 创建重配置逻辑
2.2.9. 将PHY IP连接到PLL IP Core和Reset Controller
2.2.10. 连接数据通路(Connect Datapath)
2.2.11. 模拟参数设置
2.2.12. 编译设计
2.2.13. 验证设计功能性
2.7.1. PIPE的收发器通道数据通路
2.7.2. 支持的PIPE特性
2.7.3. 如何连接PIPE Gen1和Gen2模式的TX PLL
2.7.4. 如何在 Cyclone® 10 GX收发器中实现PCI Express (PIPE)
2.7.5. PIPE的Native PHY IP参数设置
2.7.6. 用于PIPE的fPLL IP参数内核设置
2.7.7. 用于PIPE的ATX PLL IP参数设置
2.7.8. 用于PIPE的Native PHY IP端口
2.7.9. 用于PIPE的fPLL端口
2.7.10. 用于PIPE的ATX PLL端口
2.7.11. 如何对PIPE配置布局通道
2.9.1.1. 如何在 Cyclone® 10 GX收发器中实现基本(增强型PCS)收发器配置规则(Basic (Enhanced PCS) Transceiver Configuration Rules)
2.9.1.2. Basic (Enhanced PCS)的Native PHY IP参数设置
2.9.1.3. 如何在Basic Enhanced PCS中使能低延迟
2.9.1.4. 增强的PCS FIFO操作
2.9.1.5. TX数据比特滑移(TX Data Bitslip)
2.9.1.6. TX数据极性反转
2.9.1.7. RX数据比特滑移(RX Data Bitslip)
2.9.1.8. RX数据极性反转
2.9.2.1. 字对齐器手动模式(Word Aligner Manual Mode)
2.9.2.2. 字对齐器同步状态机模式
2.9.2.3. RX比特滑移(RX Bit Slip)
2.9.2.4. RX极性反转
2.9.2.5. RX比特反转(RX Bit Reversal)
2.9.2.6. RX字节反转(RX Byte Reversal)
2.9.2.7. 基本(单宽度)模式下的速率匹配FIFO
2.9.2.8. Rate Match FIFO Basic (Double Width)模式
2.9.2.9. 8B/10B编码器和解码器(8B/10B Encoder and Decoder)
2.9.2.10. 8B/10B TX差异控制
2.9.2.11. 如何在Basic模式下使能低延迟
2.9.2.12. TX比特滑移(TX Bit Slip)
2.9.2.13. TX极性反转
2.9.2.14. TX比特反转(TX Bit Reversal)
2.9.2.15. TX字节反转(TX Byte Reversal)
2.9.2.16. 如何在 Cyclone® 10 GX收发器中实现基本收发器配置规则和带速率匹配的基本收发器配置规则
2.9.2.17. Basic,速率匹配配置的Basic的Native PHY IP参数设置
6.1. 重新配置通道和PLL块
6.2. 与重配置接口进行交互
6.3. 配置文件
6.4. 多个重配置Profile
6.5. 嵌入式重配置Streamer
6.6. 仲裁
6.7. 动态重配置的建议
6.8. 执行动态重配置的步骤
6.9. 直接重配置流程
6.10. Native PHY IP或PLL IP核指导型重配置流程
6.11. 特殊情况的重配置流程
6.12. 更改PMA模拟参数
6.13. 端口和参数
6.14. 动态重配置接口跨多个IP块合并
6.15. 嵌入式调试功能
6.16. 使用数据码型生成器和检查器
6.17. 时序收敛建议
6.18. 不支持的功能
6.19. Cyclone® 10 GX收发器寄存器映射
8.7.1. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
8.7.2. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
8.7.3. XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
8.7.4. XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
8.7.5. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
8.7.6. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
8.7.7. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
8.7.8. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
仅对英特尔可见 — GUID: jbd1486507184657
Ixiasoft
2.7.5. PIPE的Native PHY IP参数设置
Gen1 PIPE | Gen2 PIPE | |
---|---|---|
Parameter | ||
Message level for rule violations | Error | Error |
Common PMA Options | ||
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver | Gen1: 0_9V | Gen2: 0_9V |
Transceiver link type | Gen1: sr | Gen2: sr |
Datapath Options | ||
Transceiver configuration rules | Gen1 PIPE | Gen2 PIPE |
PMA configuration rules | Basic | Basic |
Transceiver mode | TX / RX Duplex | TX / RX Duplex |
Number of data channels | Gen1 x1: 1 channel Gen1 x2: 2 channels Gen1 x4: 4 channels |
Gen2 x1: 1 channel Gen2 x2: 2 channels Gen2 x4: 4 channels |
Data rate | 2.5 Gbps | 5 Gbps |
Enable datapath and interface reconfiguration | Optional | Optional |
Enable simplified data interface | Optional 21 | Optional 21 |
Provide separate interface for each channel | Optional | Optional |
Gen1 PIPE | Gen2 PIPE | |
---|---|---|
TX Bonding Options | ||
TX channel bonding mode | Nonbonded (x1) PMA & PCS Bonding (x2 and x4) |
Nonbonded (x1) PMA & PCS Bonding (x2 and x4) |
PCS TX channel bonding master | Auto 22 | Auto 22 |
Default PCS TX channel bonding master | Gen1 x1: Channel 0 Gen1 x2: Channel 1 Gen1 x4: Channel 2 |
Gen1 x1: Channel 0 Gen1 x2: Channel 1 Gen1 x4: Channel 2 |
TX PLL Options | ||
TX local clock division factor | 1 | 1 |
Number of TX PLL clock inputs per channel | 1 | 1 |
Initial TX PLL clock input selection | 0 | 0 |
TX PMA Optional Ports | ||
Enable tx_analog_reset_ack port | Optional | Optional |
Enable tx_pma_clkout port | Optional | Optional |
Enable tx_pma_div_clkout port | Optional | Optional |
tx_pma_div_clkout division factor | Optional | Optional |
Enable tx_pma_elecidle port | Off | Off |
Enable rx_seriallpbken port | Off | Off |
Gen1 PIPE | Gen2 PIPE | |
---|---|---|
RX CDR Options | ||
Number of CDR reference clocks | 1 | 1 |
Selected CDR reference clock | 0 | 0 |
Selected CDR reference clock frequency | 100, 125 MHz | 100, 125 MHz |
PPM detector threshold | 1000 | 1000 |
Equalization | ||
CTLE adaptation mode | Manual | Manual |
DFE adaptation mode | Disabled | Disabled |
Number of fixed dfe taps | NA | NA |
RX PMA Optional Ports | ||
Enable rx_analog_reset_ack port | Optional | Optional |
Enable rx_pma_clkout port | Optional | Optional |
Enable rx_pma_div_clkout port | Optional | Optional |
rx_pma_div_clkout division factor | Optional | Optional |
Enable rx_pma_clkslip port | Optional | Optional |
Enable rx_is_lockedtodata port | Optional | Optional |
Enable rx_is_lockedtoref port | Optional | Optional |
Enable rx_set_locktodata and rx_set_locktoref ports | Optional | Optional |
Enable rx_seriallpbken port | Optional | Optional |
Enable PRBS Verifier Control and Status ports | Optional | Optional |
参数 | Gen1 PIPE | Gen2 PIPE |
---|---|---|
Standard PCS configurations | ||
Standard PCS / PMA interface width | 10 | 10 |
FPGA Fabric / Standard TX PCS interface width | 8, 16 | 16 |
FPGA Fabric / Standard RX PCS interface width | 8, 16 | 16 |
Enable Standard PCS low latency mode | Off | Off |
Standard PCS FIFO | ||
TX FIFO mode | low_latency | low_latency |
RX FIFO mode | low_latency | low_latency |
Enable tx_std_pcfifo_full port | Optional | Optional |
Enable tx_std_pcfifo_empty port | Optional | Optional |
Enable rx_std_pcfifo_full port | Optional | Optional |
Enable rx_std_pcfifo_empty port | Optional | Optional |
Byte Serializer and Deserializer | ||
TX byte serializer mode | Disabled, Serialize x2 | Serialize x2 |
RX byte deserializer mode | Disabled, Serialize x2 | Serialize x2 |
8B/10B Encoder and Decoder | ||
Enable TX 8B/10B encoder | Enabled | Enabled |
Enable TX 8B/10B disparity control | Enabled | Enabled |
Enable RX 8B/10B decoder | Enabled | Enabled |
Rate Match FIFO | ||
Rate Match FIFO mode | PIPE, PIPE 0ppm | PIPE, PIPE 0ppm |
RX rate match insert / delete -ve pattern (hex) | 0x0002f17c (K28.5/K28.0/) | 0x0002f17c (K28.5/K28.0/) |
RX rate match insert / delete +ve pattern (hex) | 0x000d0e83 (K28.5/K28.0/) | 0x000d0e83 (K28.5/K28.0/) |
Enable rx_std_rmfifo_full port | Optional | Optional |
Enable rx_std_rmfifo_empty port | Optional | Optional |
Word Aligner and Bit Slip | ||
Enable TX bit slip | Off | Off |
Enable tx_std_bitslipboundarysel port | Optional | Optional |
RX word aligner mode | Synchronous State Machine | Synchronous State Machine |
RX word aligner pattern length | 10 | 10 |
RX word aligner pattern (hex) | 0x0000 00000000017c (/K28.5/) | 0x0000 00000000017c (/K28.5/) |
Number of word alignment patterns to achieve sync | 3 | 3 |
Number of invalid data words to lose sync | 16 | 16 |
Number of valid data words to decrement error count | 15 | 15 |
Enable rx_std_wa_patternalign port | Optional | Optional |
Enable rx_std_wa_a1a2size port | Off | Off |
Enable rx_std_bitslipboundarysel port | Optional | Optional |
Enable rx_bitslip port | Off | Off |
比特倒转与极性反转(Bit Reversal and Polarity Inversion) | ||
Enable TX bit reversal | Off | Off |
Enable TX byte reversal | Off | Off |
Enable TX polarity inversion | Off | Off |
Enable tx_polinv port | Off | Off |
Enable RX bit reversal | Off | Off |
Enable rx_std_bitrev_ena port | Off | Off |
Enable RX byte reversal | Off | Off |
Enable rx_std_byterev_ena port | Off | Off |
Enable RX polarity inversion | Off | Off |
Enable rx_polinv port | Off | Off |
Enable rx_std_signaldetect port | Optional | Optional |
PCIe Ports | ||
Enable PCIe dynamic datarate switch ports | Off | Enabled |
Enable PCIe pipe_hclk_in and pipe_hclk_out ports | Enabled | Enabled |
Enable PCIe electrical idle control and status ports | Enabled | Enabled |
Enable PCIe pipe_rx_polarity port | Enabled | Enabled |
Dynamic reconfiguration | ||
Enable dynamic reconfiguration | Disabled | Disabled |
注: Simplified Interface使能时,最左侧列中的信号将自动映射到128-bit tx_parallel_data字的子集。
21 请参考来了解简化数据接口使能时的比特设置。
22 此参数的设置取决于布局。在AUTO模式下,Native PHY IP Parameter Editor将选择配置的最中间通道作为默认的PCS TX channel bonding master。您必须确保将所选通道物理布局为收发器bank的Ch1或Ch4。否则,对PCS TX channel bonding master使用手动选择来选择可以物理布局在收发器bank的Ch1或Ch4的通道。关于详细信息,请参考“如何对PIPE配置布局通道”一节。