Intel® Cyclone® 10 GX收发器PHY用户指南

ID 683054
日期 12/28/2017
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2.5.4. 用于Interlaken的Native PHY IP参数设置

本节包含此协议的建议参数值。请参考 Using the Cyclone® 10 GX Transceiver Native PHY IP Core 来了解参数值的完整范围。
表 68.  常规参数和数据通道参数

参数

Message level for rule violations

error

warning

Transceiver configuration rules

Interlaken

PMA configuration rules basic

Transceiver mode

TX / RX Duplex

TX Simplex

RX Simplex

Number of data channels

1 to 12

Data rate

Up to 12.5 Gbps for GX devices

(取决于Enhanced PCS到PMA接口宽度选择)

Enable datapath and interface reconfiguration

On / Off

Enable simplified data interface

On / Off

Provide separate interface for each channel

On / Off

表 69.  TX PMA参数

参数

TX channel bonding mode

Not bonded

PMA-only bonding

PMA and PCS bonding

PCS TX channel bonding master

如果TX channel bonding mode设置成PMA and PCS bonding,那么:

Auto, 0, 1, 2, 3,...,[Number of data channels – 1]

Actual PCS TX channel bonding master

如果TX channel bonding mode设置成PMA and PCS bonding,那么:

0, 1, 2, 3,...,[Number of data channels – 1]

TX local clock division factor

如果TX channel bonding mode没有绑定,那么:

1, 2, 4, 8

Number of TX PLL clock inputs per channel

如果TX channel bonding mode没有绑定,那么:

1, 2, 3, 4

Initial TX PLL clock input selection

0

Enable tx_pma_clkout port

On / Off

Enable tx_pma_div_clkout port

On / Off

tx_pma_div_clkout division factor

Enable tx_pma_div_clkout portOn时,那么:

Disabled, 1, 2, 33, 40, 66

Enable tx_pma_elecidle port

On / Off

Enable rx_seriallpbken port

On / Off

表 70.  RX PMA参数

参数

Number of CDR reference clocks

1 to 5

Selected CDR reference clock

0 to 4

Selected CDR reference clock frequency

选择Quartus Prime软件定义的合法范围

PPM detector threshold

100, 300, 500, 1000

CTLE adaptation mode

manual,

Enable rx_pma_clkout port

On / Off

Enable rx_pma_div_clkout port

On / Off

rx_pma_div_clkout division factor

Enable rx_pma_div_clkout portOn时,那么:

Disabled, 1, 2, 33, 40, 66

Enable rx_pma_clkslip port

On / Off

Enable rx_is_lockedtodata port

On / Off

Enable rx_is_lockedtoref port

On / Off

Enable rx_set_locktodata and rx_set_locktoref ports

On / Off

Enable rx_seriallpbken port

On / Off

Enable PRBS verifier control and status ports

On / Off

表 71.  Enhanced PCS参数

参数

Enhanced PCS / PMA interface width

32, 40, 64

FPGA fabric / Enhanced PCS interface width

67

Enable 'Enhanced PCS' low latency mode

当PMA接口宽度为32且数据速率的预置变化(preset variation)为10.3125 Gbps或6.25 Gbps时可开启此参数:否则为Off

Enable RX/TX FIFO double-width mode

Off

TX FIFO mode

Interlaken

TX FIFO partially full threshold

8 to 15

TX FIFO partially empty threshold

1 to 8

Enable tx_enh_fifo_full port

On / Off

Enable tx_enh_fifo_pfull port

On / Off

Enable tx_enh_fifo_empty port

On / Off

Enable tx_enh_fifo_pempty port

On / Off

RX FIFO mode

Interlaken

RX FIFO partially full threshold

from 10-29 (不少于pempty_threshold+8)

RX FIFO partially empty threshold

2 to 10

Enable RX FIFO alignment word deletion (Interlaken)

On / Off

Enable RX FIFO control word deletion (Interlaken)

On / Off

Enable rx_enh_data_valid port

On / Off

Enable rx_enh_fifo_full port

On / Off

Enable rx_enh_fifo_pfull port

On / Off

Enable rx_enh_fifo_empty port

On / Off

Enable rx_enh_fifo_pempty port

On / Off

Enable rx_enh_fifo_del port (10GBASE-R)

Off

Enable rx_enh_fifo_insert port (10GBASE-R)

Off

Enable rx_enh_fifo_rd_en port

On

Enable rx_enh_fifo_align_val port (Interlaken)

On / Off

Enable rx_enh_fifo_align_clr port (Interlaken)

On

表 72.  Interlaken帧生成器参数(Interlaken Frame Generator Parameters)

参数

Enable Interlaken frame generator

On

Frame generator metaframe length

5 to 8192 (Intel建议最小元帧长度为128)

Enable frame generator burst control

On

Enable tx_enh_frame port

On

Enable tx_enh_frame_diag_status port

On

Enable tx_enh_frame_burst_en port

On

表 73.  Interlaken帧同步器参数(Interlaken Frame Synchronizer Parameters)

参数

Enable Interlaken frame synchronizer

On

Frame synchronizer metaframe length

5 to 8192 (Intel建议最小元帧长度为128)

Enable rx_enh_frame port

On

Enable rx_enh_frame_lock port

On / Off

Enable rx_enh_frame_diag_status port

On / Off

表 74.  Interlaken CRC-32 Generator and Checker Parameters

参数

Enable Interlaken TX CRC-32 generator

On

Enable Interlaken TX CRC-32 generator error insertion

On / Off

Enable Interlaken RX CRC-32 checker

On

Enable rx_enh_crc32_err port

On / Off

表 75.  加扰器和解扰器参数(Scrambler and Descrambler Parameters)

参数

Enable TX scrambler (10GBASE-R / Interlaken)

On

TX scrambler seed (10GBASE-R / Interlaken)

0x1 to 0x3FFFFFFFFFFFFFF

Enable RX descrambler (10GBASE-R / Interlaken)

On

表 76.  Interlaken Disparity Generator and Checker Parameters

Parameter

Value

Enable Interlaken TX disparity generator

On

Enable Interlaken RX disparity checker

On

Enable Interlaken TX random disparity bit

On / Off

表 77.  模块同步参数(Block Sync Parameters)

参数

Enable RX block synchronizer

On

Enable rx_enh_blk_lock port

On / Off

表 78.  齿轮箱参数(Gearbox Parameters)

参数

Enable TX data bitslip

Off

Enable TX data polarity inversion

On / Off

Enable RX data bitslip

Off

Enable RX data polarity inversion

On / Off

Enable tx_enh_bitslip port

Off

Enable rx_bitslip port

Off

表 79.  动态重配置参数

参数

Enable dynamic reconfiguration

On / Off

Share reconfiguration interface

On / Off

Enable Altera Debug Master Endpoint

On / Off

Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE

On / Off

Enable capability registers

On / Off

Set user-defined IP indentifier:

0 to 255

Enable control and status registers

On / Off

Enable prbs soft accumulators

On / Off

表 80.  配置文件参数

参数

Configuration file prefix

Generate SystemVerilog package file

On / Off

Generate C header file

On / Off

Generate MIF (Memory Initialization File)

On / Off

Include PMA analog settings in configuration files

On / Off

表 81.  配置设置文件参数(Configuration Profiles Parameters)

参数

Enable multiple reconfiguration profiles

On / Off

Enable embedded reconfiguration streamer

On / Off

Generate reduced reconfiguration files

On / Off

Number of reconfiguration profiles

1 to 8

Selected reconfiguration profile

1 to 7