仅对英特尔可见 — GUID: mtr1430268751237
Ixiasoft
2.4.2.1. 高速时钟域(High-Speed Clock Domains)
2.4.2.2. 重构环路(Restructuring Loops)
2.4.2.3. 控制信号反压(Control Signal Backpressure)
2.4.2.4. 使用FIFO状态信号的流程控制
2.4.2.5. 包含skid缓冲器的流程控制
2.4.2.6. Read-Modify-Write存储器
2.4.2.7. 计数器和累加器
2.4.2.8. 状态机
2.4.2.9. 储存器
2.4.2.10. DSP模块
2.4.2.11. 一般逻辑
2.4.2.12. 求模与除法
2.4.2.13. 复位
2.4.2.14. 硬件重用
2.4.2.15. 算法要求
2.4.2.16. FIFO
2.4.2.17. 三元加法器(Ternary Adders)
5.2.1. 不足的寄存器(insufficient Registers)
5.2.2. 短路径/长路径(short path/long path)
5.2.3. 快进限制(Fast Forward Limit)
5.2.4. 环路(loop)
5.2.5. 每个时钟域一个关键链
5.2.6. 相关时钟组中的关键链
5.2.7. 复杂的关键链
5.2.8. 延伸到可定位的节点
5.2.9. 域边界入口和域边界出口(Domain Boundary Entry and Domain Boundary Exit)
5.2.10. 包括双时钟存储器的关键链
5.2.11. 关键链比特和总线
5.2.12. 延迟线
仅对英特尔可见 — GUID: mtr1430268751237
Ixiasoft
8.1. 附录A:可参数化的流水线模块
下面的实例显示了Verilog HDL,SystemVerilog和VHDL中可参数化的流水线模块。在顶层I/O和时钟域边界上使用这些代码模块来更改电路的延迟。
可参数化的Hyper-Pipelining Verilog HDL模块
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION off" *) module hyperpipe #(parameter CYCLES = 1, parameter WIDTH = 1) ( input clk, input [WIDTH-1:0] din, output [WIDTH-1:0] dout ); generate if (CYCLES==0) begin : GEN_COMB_INPUT assign dout = din; end else begin : GEN_REG_INPUT integer i; reg [WIDTH-1:0] R_data [CYCLES-1:0]; always @ (posedge clk) begin R_data[0] <= din; for(i = 1; i < CYCLES; i = i + 1) R_data[i] <= R_data[i-1]; end assign dout = R_data[CYCLES-1]; end endgenerate endmodule
可参数化的Hyper-Pipelining Verilog HDL实例
hyperpipe # ( .CYCLES ( ), .WIDTH ( ) ) hp ( .clk ( ), .din ( ), .dout ( ) );
可参数化的Hyper-Pipelining SystemVerilog模块
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION off" *) module hyperpipe #(parameter int CYCLES = 1, PACKED_WIDTH = 1, UNPACKED_WIDTH = 1 ) ( input clk, input [PACKED_WIDTH-1:0] din [UNPACKED_WIDTH-1:0], output [PACKED_WIDTH-1:0] dout [UNPACKED_WIDTH-1:0] ); generate if (CYCLES == 0) begin : GEN_COMB_INPUT assign dout = din; end else begin : GEN_REG_INPUT integer i; reg [PACKED_WIDTH-1:0] R_data [CYCLES-1:0][UNPACKED_WIDTH-1:0]; always_ff@(posedge clk) begin R_data[0] <= din; for(i = 1; i < CYCLES; i = i + 1) R_data[i] <= R_data[i-1]; end assign dout = R_data[CYCLES-1]; end endgenerate endmodule : hyperpipe
可参数化的Hyper-Pipelining SystemVerilog实例
// Quartus Prime SystemVerilog Template // // Hyper-Pipelining Module Instantiation hyperpipe # ( .CYCLES ( ), .PACKED_WIDTH ( ), .UNPACKED_WIDTH ( ) ) hp ( .clk ( ), .din ( ), .dout ( ) );
可参数化的Hyper-Pipelining VHDL实体
library IEEE; use IEEE.std_logic_1164.all; library altera; use altera.altera_syn_attributes.all; entity hyperpipe is generic ( CYCLES : integer := 1; WIDTH : integer := 1 ); port ( clk : in std_logic; din : in std_logic_vector (WIDTH - 1 downto 0); dout : out std_logic_vector (WIDTH - 1 downto 0) ); end entity; architecture arch of hyperpipe is type hyperpipe_t is array(CYCLES-1 downto 0) of std_logic_vector(WIDTH-1 downto 0); signal HR : hyperpipe_t; -- Prevent large hyperpipes from going into memory-based altshift_taps, -- since that won't take advantage of Hyper-Registers attribute altera_attribute of HR : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION off"; begin wire : if CYCLES = 0 GENERATE -- The 0 bit is just a pass-thru, when CYCLES is set to 0 dout <= din; end generate wire; hp : if CYCLES > 0 GENERATE process (clk) begin if (clk'event and clk = '1')then HR <= HR(HR'high-1 downto 0) & din; end if; end process; dout <= HR(HR'high); end generate hp; end arch;
可参数化的Hyper-Pipelining VHDL实例
-- Template Declaration component hyperpipe generic ( CYCLES : integer; WIDTH : integer ); port ( clk : in std_logic; din : in std_logic_vector(WIDTH - 1 downto 0); dout : out std_logic_vector(WIDTH - 1 downto 0) ); end component; -- Instantiation Template: hp : hyperpipe generic map ( CYCLES => , WIDTH => ) port map ( clk => , din => , dout => );