仅对英特尔可见 — GUID: mwh1417734823782
Ixiasoft
2.5.1.1. Report Fmax Summary(报告Fmax汇总)
2.5.1.2. Report Timing(报告时序)
2.5.1.3. Report Timing By Source Files(按源文件报告时序)
2.5.1.4. Report Data Delay(报告数据延迟)
2.5.1.5. Report Net Delay(报告网络延迟)
2.5.1.6. Report Clocks and Clock Network(报告时钟和时钟网络)
2.5.1.7. Report Clock Transfers(报告时钟传输)
2.5.1.8. Report Metastability(报告亚稳定性)
2.5.1.9. Report CDC Viewer(报告CDC Viewer)
2.5.1.10. Report Asynchronous CDC(报告异步CDC)
2.5.1.11. Report Logic Depth(报告逻辑深度)
2.5.1.12. Report Neighbor Paths(报告相邻路径)
2.5.1.13. Report Register Spread
2.5.1.14. Report Route Net of Interest
2.5.1.15. Report Retiming Restrictions(报告重定时限制)
2.5.1.16. Report Register Statistics(报告寄存器统计)
2.5.1.17. Report Pipelining Information(报告流水线信息)
2.5.1.18. 报告时间借用数据
2.5.1.19. Report Exceptions and Exceptions Reachability(报告异常和异常可达性)
2.5.1.20. Report Bottlenecks(报告瓶颈)
仅对英特尔可见 — GUID: mwh1417734823782
Ixiasoft
2.6.5.2.2. I/O接口时钟不确定性示例
要指定I/O接口不确定性,必须创建一个虚拟时钟,并通过引用此虚拟时钟的set_input_delay和set_output_delay命令约束输入和输出端口。
当set_input_delay或set_output_delay命令引用一个时钟端口或PLL输出时,虚拟时钟允许derive_clock_uncertainty命令对内部时钟传输和I/O接口时钟传输应用单独的时钟不确定性。
创建具有与驱动I/O端口的原始时钟相同属性的虚拟时钟,如以下示例所示:
约束I/O接口的SDC命令
# Create the base clock for the clock port create_clock -period 10 -name clk_in [get_ports clk_in] # Create a virtual clock with the same properties of the base clock # driving the source register create_clock -period 10 -name virt_clk_in # Create the input delay referencing the virtual clock and not the base # clock # DO NOT use set_input_delay -clock clk_in <delay value> # [get_ports data_in] set_input_delay -clock virt_clk_in <delay value> [get_ports data_in]