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2.5.1.1. Report Fmax Summary(报告Fmax汇总)
2.5.1.2. Report Timing(报告时序)
2.5.1.3. Report Timing By Source Files(按源文件报告时序)
2.5.1.4. Report Data Delay(报告数据延迟)
2.5.1.5. Report Net Delay(报告网络延迟)
2.5.1.6. Report Clocks and Clock Network(报告时钟和时钟网络)
2.5.1.7. Report Clock Transfers(报告时钟传输)
2.5.1.8. Report Metastability(报告亚稳定性)
2.5.1.9. Report CDC Viewer(报告CDC Viewer)
2.5.1.10. Report Asynchronous CDC(报告异步CDC)
2.5.1.11. Report Logic Depth(报告逻辑深度)
2.5.1.12. Report Neighbor Paths(报告相邻路径)
2.5.1.13. Report Register Spread
2.5.1.14. Report Route Net of Interest
2.5.1.15. Report Retiming Restrictions(报告重定时限制)
2.5.1.16. Report Register Statistics(报告寄存器统计)
2.5.1.17. Report Pipelining Information(报告流水线信息)
2.5.1.18. 报告时间借用数据
2.5.1.19. Report Exceptions and Exceptions Reachability(报告异常和异常可达性)
2.5.1.20. Report Bottlenecks(报告瓶颈)
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2.5.2. Cross-Probing with Design Assistant
The Intel® Quartus® Prime Design Assistant can automatically report any violations against a standard set of Intel FPGA-recommended design guidelines during stages of compilation. You can specify which rules you want the Design Assistant to check in your design, and customize the severity levels, thus eliminating or waiving rule checks that are not important for your design.
当您在编译期间运行Design Assistant时,Design Assistant会使用在编译期间生成的流入(瞬态)数据来检查是否存在违反规则的情况。
在Timing Analyzer中,当您在分析模式下运行 Design Assistant时,Design Assistant使用您加载的静态编译快照数据执行设计规则检查。
某些Design Assistant违规支持对相关的时序分析数据进行叉探测。交叉探测可以帮助您更快地识别根本原因并解决任何Design Assistant违规的问题。例如,对于存在设置分析违规的路径,您可以交叉探测Timing Analyzer,以识别为保持时间添加了延迟的边沿。
注: 在交叉探测Timing Analyzer之前,您必须至少通过Plan阶段运行Compiler。