仅对英特尔可见 — GUID: mwh1417737689362
Ixiasoft
2.5.1.1. Report Fmax Summary(报告Fmax汇总)
2.5.1.2. Report Timing(报告时序)
2.5.1.3. Report Timing By Source Files(按源文件报告时序)
2.5.1.4. Report Data Delay(报告数据延迟)
2.5.1.5. Report Net Delay(报告网络延迟)
2.5.1.6. Report Clocks and Clock Network(报告时钟和时钟网络)
2.5.1.7. Report Clock Transfers(报告时钟传输)
2.5.1.8. Report Metastability(报告亚稳定性)
2.5.1.9. Report CDC Viewer(报告CDC Viewer)
2.5.1.10. Report Asynchronous CDC(报告异步CDC)
2.5.1.11. Report Logic Depth(报告逻辑深度)
2.5.1.12. Report Neighbor Paths(报告相邻路径)
2.5.1.13. Report Register Spread
2.5.1.14. Report Route Net of Interest
2.5.1.15. Report Retiming Restrictions(报告重定时限制)
2.5.1.16. Report Register Statistics(报告寄存器统计)
2.5.1.17. Report Pipelining Information(报告流水线信息)
2.5.1.18. 报告时间借用数据
2.5.1.19. Report Exceptions and Exceptions Reachability(报告异常和异常可达性)
2.5.1.20. Report Bottlenecks(报告瓶颈)
仅对英特尔可见 — GUID: mwh1417737689362
Ixiasoft
2.6.5.3.1. 时钟分频器示例(-divide_by)
生成时钟的常见形式是二分频寄存器时钟分频器(divide-by-two register clock divider)。以下示例约束在二分频(divide-by-two)寄存器上创建一个半速率时钟。
create_clock -period 10ns -name clk_sys [get_ports clk_sys] create_generated_clock -name clk_div_2 -divide_by 2 -source \ [get_ports clk_sys] [get_pins reg|q]
将寄存器的时钟管脚指定为时钟源:
create_clock -period 10ns -name clk_sys [get_ports clk_sys] create_generated_clock -name clk_div_2 -divide_by 2 -source \ [get_pins reg|clk] [get_pins reg|q]
图 111. 时钟分频器(Clock Divider)
图 112. 时钟分频器波形(Clock Divider Waveform)