仅对英特尔可见 — GUID： joc1422471389222
Ixiasoft
2.2.2.2. PLL规范
| 符号 | 参数 | Min | Typ | Max | 单位 |
|---|---|---|---|---|---|
| fIN 164 | 输入时钟频率(C3，I3L速度等级) | 5 | — | 800 | MHz |
| 输入时钟频率(C4，I4速度等级) | 5 | — | 650 | MHz | |
| fINPFD | Input frequency to the PFD | 5 | — | 325 | MHz |
| fFINPFD | Fractional Input clock frequency to the PFD | 50 | — | 160 | MHz |
| fVCO 165 | PLL VCO operating range (C3, I3L speed grade) | 600 | — | 1600 | MHz |
| PLL VCO operating range (C4, I4 speed grade) | 600 | — | 1300 | MHz | |
| tEINDUTY | Input clock or external feedback clock input duty cycle | 40 | — | 60 | % |
| fOUT 166 | Output frequency for an internal global or regional clock (C3, I3L speed grade) | — | — | 650 | MHz |
| Output frequency for an internal global or regional clock (C4, I4 speed grade) | — | — | 580 | MHz | |
| fOUT_EXT 166 | Output frequency for an external clock output (C3, I3L speed grade) | — | — | 667 | MHz |
| Output frequency for an external clock output (C4, I4 speed grade) | — | — | 533 | MHz | |
| tOUTDUTY | Duty cycle for a dedicated external clock output (when set to 50%) | 45 | 50 | 55 | % |
| tFCOMP | External feedback clock compensation time | — | — | 10 | ns |
| fDYCONFIGCLK | Dynamic configuration clock for mgmt_clk and scanclk | — | — | 100 | MHz |
| tLOCK | Time required to lock from the end-of-device configuration or deassertion of areset | — | — | 1 | ms |
| tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | 1 | ms |
| fCLBW | PLL closed-loop low bandwidth | — | 0.3 | — | MHz |
| PLL closed-loop medium bandwidth | — | 1.5 | — | MHz | |
| PLL closed-loop high bandwidth 167 | — | 4 | — | MHz | |
| tPLL_PSERR | Accuracy of PLL phase shift | — | — | ±50 | ps |
| tARESET | Minimum pulse width on the areset signal | 10 | — | — | ns |
| tINCCJ 168, 169 | Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz) | — | — | 0.15 | UI (p-p) |
| Input clock cycle-to-cycle jitter (fREF < 100 MHz) | -750 | — | +750 | ps (p-p) | |
| tOUTPJ_DC 170 | Period Jitter for dedicated clock output in integer PLL (fOUT ≥ 100 MHz) | — | — | 175 | ps (p-p) |
| Period Jitter for dedicated clock output in integer PLL (fOUT < 100 Mhz) | — | — | 17.5 | mUI (p-p) | |
| tFOUTPJ_DC 170 | Period Jitter for dedicated clock output in fractional PLL (fOUT ≥ 100 MHz) | — | — | 250173, 175171 | ps (p-p) |
| Period Jitter for dedicated clock output in fractional PLL (fOUT < 100 MHz) | — | — | 25173, 17.5 171 | mUI (p-p) | |
| tOUTCCJ_DC 170 | Cycle-to-cycle Jitter for a dedicated clock output in integer PLL (fOUT ≥ 100 MHz) | — | — | 175 | ps (p-p) |
| Cycle-to-cycle Jitter for a dedicated clock output in integer PLL (fOUT < 100 MHz) | — | — | 17.5 | mUI (p-p) | |
| tFOUTCCJ_DC 170 | Cycle-to-cycle Jitter for a dedicated clock output in fractional PLL (fOUT ≥ 100 MHz) | — | — | 250173, 175 171 | ps (p-p) |
| Cycle-to-cycle Jitter for a dedicated clock output in fractional PLL (fOUT < 100 MHz) | — | — | 25173, 17.5 171 | mUI (p-p) | |
| tOUTPJ_IO , 170, 172 | Period Jitter for a clock output on a regular I/O in integer PLL (fOUT ≥ 100 MHz) | — | — | 600 | ps (p-p) |
| Period Jitter for a clock output on a regular I/O in integer PLL (fOUT < 100 MHz) | — | — | 60 | mUI (p-p) | |
| tFOUTPJ_IO 170, 172, 173 | Period Jitter for a clock output on a regular I/O in fractional PLL (fOUT ≥ 100 MHz) | — | — | 600 | ps (p-p) |
| Period Jitter for a clock output on a regular I/O in fractional PLL (fOUT < 100 MHz) | — | — | 60 | mUI (p-p) | |
| tOUTCCJ_IO 170, 172 | Cycle-to-cycle Jitter for a clock output on a regular I/O in integer PLL (fOUT ≥ 100 MHz) | — | — | 600 | ps (p-p) |
| Cycle-to-cycle Jitter for a clock output on a regular I/O in integer PLL (fOUT < 100 MHz) | — | — | 60 | mUI (p-p) | |
| tFOUTCCJ_IO 170, 172, 173 | Cycle-to-cycle Jitter for a clock output on a regular I/O in fractional PLL (fOUT ≥ 100 MHz) | — | — | 600 | ps (p-p) |
| Cycle-to-cycle Jitter for a clock output on a regular I/O in fractional PLL (fOUT < 100 MHz) | — | — | 60 | mUI (p-p) | |
| tCASC_OUTPJ_DC 170, 174 | Period Jitter for a dedicated clock output in cascaded PLLs (fOUT ≥ 100 MHz) | — | — | 175 | ps (p-p) |
| Period Jitter for a dedicated clock output in cascaded PLLS (fOUT < 100 MHz) | — | — | 17.5 | mUI (p-p) | |
| dKBIT | Bit number of Delta Sigma Modulator (DSM) | 8 | 24 | 32 | Bits |
| kVALUE | Numerator of Fraction | 128 | 8388608 | 2147483648 | — |
| fRES | Resolution of VCO frequency (fINPFD = 100 MHz) | 390625 | 5.96 | 0.023 | Hz |
164 此规范在Quartus II中受I/O最大频率限制。I/O最大频率对于每种I/O标准是各不相同的。
165 Quartus II中编译报告的PLL汇总部分报告的VCO频率考虑到VCO后缩放计数器K值。因此，如果计数器K的值为2，那么报告的频率能够低于fVCO规范。
166 此规范受限于PLL的I/O fMAX和fOUT两者中较低的一个。
167 在外部反馈模式下不支持高带宽PLL设置。
168 高输入抖动直接影响PLL输出抖动。要达到低PLL输出时钟抖动，就必须提供一个低于120 ps的干净时钟源。
169 当N=1时，应用fREF is fIN/N规范。
170 10–12 (14 sigma, 99.99999999974404%置信水平)概率水平的峰峰抖动(peak-to-peak jitter)。当应用30 ps的输入抖动时，输出抖动规范适用于PLL的固有抖动。外部存储器接口时钟输出抖动规范使用一个不同的测量方法，请参考“Arria V GZ I/O管脚上的最坏情况DCD”表。
171 此规范仅涵盖用于低带宽的小数分频。对于小数分频值范围0.20–0.80，fVCO必须≥1200 MHz。
172 外部存储器接口时钟输出抖动规范使用一个不同的测量方法，请参考“Arria V GZ器件的存储器输出时钟抖动规范”表。
173 此规范仅涵盖用于低带宽的小数分频。对于小数分频值范围0.05–0.95，fVCO必须≥1000 MHz。
174 级联PLL规范仅应用在以下条件：
a. Upstream PLL: 0.59Mhz ≤ Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz