仅对英特尔可见 — GUID: mcn1419933730000
Ixiasoft
1.2.2.2. PLL规范
符号 | 参数 | 条件 | 最小值 | 典型值 | 最大值 | 单位 |
---|---|---|---|---|---|---|
fIN | Input clock frequency | -3速度等级 | 5 | — | 800 61 | MHz |
-4速度等级 | 5 | — | 80061 | MHz | ||
-5速度等级 | 5 | — | 75061 | MHz | ||
-6速度等级 | 5 | — | 62561 | MHz | ||
fINPFD | Integer input clock frequency to the phase frequency detector (PFD) | — | 5 | — | 325 | MHz |
fFINPFD | Fractional input clock frequency to the PFD | — | 50 | — | 160 | MHz |
fVCO 62 | PLL voltage-controlled oscillator (VCO) operating range | -3速度等级 | 600 | — | 1600 | MHz |
-4速度等级 | 600 | — | 1600 | MHz | ||
-5速度等级 | 600 | — | 1600 | MHz | ||
-6速度等级 | 600 | — | 1300 | MHz | ||
tEINDUTY | Input clock or external feedback clock input duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal global or regional clock | -3速度等级 | — | — | 500 63 | MHz |
-4速度等级 | — | — | 50063 | MHz | ||
-5速度等级 | — | — | 50063 | MHz | ||
-6速度等级 | — | — | 40063 | MHz | ||
fOUT_EXT | Output frequency for external clock output | -3速度等级 | — | — | 67063 | MHz |
-4速度等级 | — | — | 67063 | MHz | ||
-5速度等级 | — | — | 62263 | MHz | ||
-6速度等级 | — | — | 50063 | MHz | ||
tOUTDUTY | Duty cycle for external clock output (when set to 50%) | — | 45 | 50 | 55 | % |
tFCOMP | External feedback clock compensation time | — | — | — | 10 | ns |
tDYCONFIGCLK | Dynamic configuration clock for mgmt_clk and scanclk | — | — | — | 100 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of areset | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
fCLBW | PLL closed-loop bandwidth | 低 | — | 0.3 | — | MHz |
中 | — | 1.5 | — | MHz | ||
高64 | — | 4 | — | MHz | ||
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on the areset signal | — | 10 | — | — | ns |
tINCCJ 65 66 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.15 | UI (p-p) |
FREF < 100 MHz | — | — | ±750 | ps (p-p) | ||
tOUTPJ_DC 67 | Period jitter for dedicated clock output in integer PLL | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tFOUTPJ_DC 67 | Period jitter for dedicated clock output in fractional PLL | FOUT ≥ 100 MHz | — | — | 250 68, 175 69 | ps (p-p) |
FOUT < 100 MHz | — | — | 2568, 17.569 | mUI (p-p) | ||
tOUTCCJ_DC 67 | Cycle-to-cycle jitter for dedicated clock output in integer PLL | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tFOUTCCJ_DC 67 | Cycle-to-cycle jitter for dedicated clock output in fractional PLL | FOUT ≥ 100 MHz | — | — | 25068, 17569 | ps (p-p) |
FOUT < 100 MHz | — | — | 2568, 17.569 | mUI (p-p) | ||
tOUTPJ_IO 67 70 | Period jitter for clock output on a regular I/O in integer PLL | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tFOUTPJ_IO 67 68 70 | Period jitter for clock output on a regular I/O in fractional PLL | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ_IO 67 70 | Cycle-to-cycle jitter for clock output on a regular I/O in integer PLL | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tFOUTCCJ_IO 67 68 70 | Cycle-to-cycle jitter for clock output on a regular I/O in fractional PLL | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tCASC_OUTPJ_DC 67 71 | Period jitter for dedicated clock output in cascaded PLLs | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tDRIFT | Frequency drift after PFDENA is disabled for a duration of 100 µs | — | — | — | ±10 | % |
dKBIT | Bit number of Delta Sigma Modulator (DSM) | — | 8 | 24 | 32 | bits |
kVALUE | Numerator of fraction | — | 128 | 8388608 | 2147483648 | — |
fRES | Resolution of VCO frequency | fINPFD = 100 MHz | 390625 | 5.96 | 0.023 | Hz |
相关信息
61 此规范在 Quartus® II软件中受I/O最大频率限制。最大I/O频率对于每种I/O标准是各不相同的。
62 Quartus® II软件报告的VCO频率考虑到VCO后缩放计数器K值。因此,如果计数器K的值为2,那么报告的频率能够低于fVCO规范。
63 此规范受限于PLL的I/O fMAX和FOUT两者中较低的一个。
64 在外部反馈模式中不支持高带宽PLL设置。
65 高输入抖动直接影响PLL输出抖动。要达到低PLL输出时钟抖动,就必须提供一个低于120 ps的干净时钟源。
66 FREF等于fIN/N,当N = 1时应用规范。
67 10–12 (14 sigma, 99.99999999974404%置信水平)概率水平的峰峰抖动(peak-to-peak jitter)。当应用30 ps的输入抖动时,输出抖动规范适用于PLL的固有抖动。外部存储器接口时钟输出抖动规范使用一个不同的测量方法,请参考“ Arria® V器件的存储器输出时钟抖动”表。
68 此规范仅涵盖用于低带宽的小数分频。对于小数分频值范围0.05–0.95,fVCO必须≥1000 MHz。
69 此规范仅涵盖用于低带宽的小数分频。对于小数分频值范围0.20–0.80,fVCO必须≥1200 MHz。
70 外部存储器接口时钟输出抖动规范使用一个不同的测量方法,在 Arria® V器件的存储器输出时钟抖动规范表中可以找到。
71 级联PLL规范仅应用在以下条件:
- Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
- Downstream PLL: Downstream PLL BW > 2 MHz