仅对英特尔可见 — GUID： bhc1411116943785
Ixiasoft
4.4.4. 时钟相关性
这一部分介绍了器件时钟、链路时钟、帧时钟和本地多帧时钟之间的时钟相关性。
实例1
Targeted Device with LMF=222, K=16 and Data rate = 6.5 Gbps
Device Clock Selected = 325 MHz (obtained during IP core generation)
Link Clock = 6.5 GHz/40 = 162.5 MHz
Frame Clock = 6.5 GHz/(10x2) = 325 MHz
Local Multiframe Clock = 325 MHz / 16 = 20.3125 MHz
SYSREF Frequency = Local Multiframe Clock / n; (n = integer; 1, 2, …)
Local Multiframe Clock Counter = (F × K/4) = (2×16/4) = 8 link clocks 24
实例 2
Targeted Device with LMF=244, K=16 and Data rate = 5.0 Gbps
Device Clock Selected = 125 MHz (在IP内核生成期间得到)
Link Clock = 5 GHz/40 = 125 MHz 25
Frame Clock = 5 GHz /(10×4) = 125 MHz 25
Local Multiframe Clock = 125 MHz / 16 = 7.8125 MHz
SYSREF Frequency = Local Multiframe Clock / n; (n = 整数; 1, 2, …)
Local Multiframe Clock Counter = (F × K/4) = (4×16/4) = 16 link clocks 24
实例3
Targeted Device with LMF=421, K=32 and Data rate = 10.0 Gbps
Device Clock Selected = 250 MHz (在IP内核生成期间得到)
Link Clock = 10 GHz/40 = 250 MHz
Frame Clock = 10 GHz/(10×1) = 1 GHz 26
Local Multiframe Clock = 1 GHz / 32 = 31.25 MHz
SYSREF Frequency = Local Multiframe Clock / n; (n = 整数; 1, 2, …)
Local Multiframe Clock Counter = (F × K/4) = (1×32/4) = 8 link clocks 24
实例4 (当F=3时，仅用于 Intel® Stratix® 10器件)
Targeted Device with LMF=883, K=32 and Data rate = 12.0 Gbps
Device Clock Selected = 300 MHz (在IP内核生成期间得到)
Link Clock = 12 GHz/40 = 300 MHz
Frame Clock = 12 GHz/(10×3) = 400 MHz 27
Local Multiframe Clock = 400 MHz / 32 = 12.5 MHz
SYSREF Frequency = Local Multiframe Clock / n; (n = 整数; 1, 2, …)
Local Multiframe Clock Counter = (F × K/4) = (3×32/4) = 24 link clocks 24
24 八个链路时钟意味着本地多帧时钟从0到7进行计数，然后环回到0。
26 在该实例中，帧时钟在FPGA架构中可能无法运行超过1 GHz的数据速率 。设计实例中的JESD204B传输层支持运行1/2速率(1 GHz/2 = 500 MHz)的数据流，两倍数据总线宽度或者1/4(1GHz/4 = 250MHz)的数据流，四倍数据总线宽度的数据流。
27 设计实例中的JESD204B传输层运行半速率的数据流(400 MHz/2 = 200 MHz)，两倍的数据总线宽度。