Intel® Stratix® 10器件数据表

ID 683181
日期 12/02/2019
Public
文档目录

I/O PLL规范

表 28.   Intel® Stratix® 10器件的I/O PLL规范
符号 参数 条件 Min Typ Max 单位
fIN Input clock frequency –1 speed grade 10 1,100 MHz
–2 speed grade 10 900 48 MHz
–3 speed grade 10 750 48 MHz
fINPFD Input clock frequency to the PFD 10 325 MHz
fVCO PLL VCO operating range –1 speed grade 600 1,600 MHz
–2 speed grade 600 1,434 MHz
–3 speed grade 600 1,280 49 MHz
fCLBW PLL closed-loop bandwidth 0.5 10 MHz
tEINDUTY Input clock or external feedback clock input duty cycle 40 60 %
fOUT Output frequency for internal clock (C counter) –1 speed grade 1,100 MHz
–2 speed grade 900 MHz
–3 speed grade 750 MHz
fOUT_EXT Output frequency for external clock output –1 speed grade 800 MHz
–2 speed grade 720 MHz
–3 speed grade 650 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) 45 50 55 %
tFCOMP External feedback clock compensation time 5 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk 200 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 1 ms
tPLL_PSERR Accuracy of PLL phase shift ±50 ps
tARESET Minimum pulse width on the areset signal 10 ns
tINCCJ 50 51 Input clock cycle-to-cycle jitter FREF ≥ 100 MHz 0.15 UI (p-p)
FREF < 100 MHz ±750 ps (p-p)
tOUTPJ_DC Period jitter for dedicated clock output FOUT ≥ 100 MHz 175 ps (p-p)
FOUT < 100 MHz 17.5 mUI (p-p)
tOUTCCJ_DC Cycle-to-cycle jitter for dedicated clock output FOUT ≥ 100 MHz 175 ps (p-p)
FOUT < 100 MHz 17.5 mUI (p-p)
tOUTPJ_IO Period jitter for clock output on the regular I/O FOUT ≥ 100 MHz 600 ps (p-p)
FOUT < 100 MHz 60 mUI (p-p)
tOUTCCJ_IO 52 Cycle-to-cycle jitter for clock output on the regular I/O FOUT ≥ 100 MHz 600 ps (p-p)
FOUT < 100 MHz 60 mUI (p-p)
tCASC_OUTPJ_DC Period jitter for dedicated clock output in cascaded PLLs through dedicated cascade path and core clock fabric FOUT ≥ 100 MHz 175 ps (p-p)
FOUT < 100 MHz 17.5 mUI (p-p)
48 这一规范受到I/O最大频率的限制。每个I/O标准最大可实现的I/O频率不同,这取决于设计以及系统的具体因素。确保设计中适当的时序收敛,并且根据具体的设计和系统设置来执行HSPICE/IBIS仿真,以确定在您的系统中能达到的最大频率。
49 此规范仅适用于使用IOPLL Intel® FPGA IP core对I/O PLL进行例化的情况。在使用LVDS SERDES Intel® FPGA IP core,PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core,External Memory Interfaces Intel Stratix 10 FPGA IP core和High Bandwidth Memory (HBM-2) Interface Intel® FPGA IP core对I/O PLL进行例化的情况, fVCO的最大值1,250 MHz。
50 高输入抖动直接影响PLL输出抖动。要达到低PLL输出时钟抖动,您必须提供一个抖动< 120 ps的干净时钟源。
51 FREF为fIN/N,当N = 1时,规范适用。
52 外部存储器接口时钟输出抖动规范使用不同的测量方法,这些方法可在器件的存储器输出时钟抖动规范表中找到。