仅对英特尔可见 — GUID: mcn1441706181503
Ixiasoft
小数分频PLL规范(Fractional PLL Specifications)
符号 | 参数 | 条件 | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | — | 29 | — | 800 | MHz |
fINPFD | Input clock frequency to the phase frequency detector (PFD) | — | 29 | — | 700 | MHz |
fVCO | PLL voltage-controlled oscillator (VCO) operating range for core applications | — | 6 | — | 14.025 | GHz |
tEINDUTY | Input clock duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal clock | — | — | — | 1 | GHz |
fDYCONFIGCLK | Dynamic configuration clock for reconfig_clk | — | — | — | 125 | MHz |
tLOCK | Time required to lock from end-of-device configuration | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
fCLBW | PLL closed-loop bandwidth | — | 0.3 | — | 4 | MHz |
tINCCJ 45, 46 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.13 | UI (p-p) |
FREF < 100 MHz | — | — | ±650 | ps (p-p) | ||
tOUTPJ | Period jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ 47 | Cycle-to-cycle jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
dKBIT | Bit number of Delta Sigma Modulator (DSM) | — | — | 32 | — | bit |
相关信息
44 这一规范受到I/O最大频率的限制。每个I/O标准最大可实现的I/O频率不同,这取决于设计以及系统的具体因素。确保设计中适当的时序收敛,并且根据具体的设计和系统设置来执行HSPICE/IBIS仿真,以确定在您的系统中能达到的最大频率。
45 高输入抖动直接影响PLL输出抖动。要达到低PLL输出时钟抖动,您必须提供一个抖动< 120 ps的干净时钟源。
46 FREF为fIN/N,当N = 1时,规范适用。
47 外部存储器接口时钟输出抖动规范使用不同的测量方法,这些方法可在器件的存储器输出时钟抖动规范表中找到。