仅对英特尔可见 — GUID: vgo1459220485027
Ixiasoft
仅对英特尔可见 — GUID: vgo1459220485027
Ixiasoft
4.1.2. RAM: 2-PORT Intel® FPGA IP参数
参数 | 合法值 | 说明 |
---|---|---|
Parameter Settings: General | ||
How will you be using the dual port RAM? | Operation mode:
|
指定如何使用双端口RAM。 |
How do you want to specify the memory size? | Type:
|
决定以字为单位还是以比特为单位来指定存储器容量。 |
Parameter Settings: Widths/ Blk Type | ||
How many words of memory? | — | 指定字的数量。 |
Use different data widths on different ports | On/Off | 指定是否在不同的端口上使用不同的数据宽度。 |
When you select With one read port and one write port or With two read/write ports, the following options are available:
|
— | 指定输入和输出端口的宽度。 |
Ram block type | Auto, MLAB, M20K, LCs | 指定存储器模块类型。可选择的存储器模块类型取决于您的目标器件。 |
Set the maximum block depth to |
|
指定最大模块深度(以字为单位)。 |
How should the memory be implemented? |
|
指定逻辑单元实现方法。
|
Parameter Settings: Clks/Rd, Byte En | ||
What clocking method would you like to use? |
|
指定要使用的时钟方法。
|
When you select With two read/write ports and Customize clocks for A and B ports clocking method, the following option is available: Emulate TDP dual clock mode |
— | 指定是否仿真TDP双时钟模式。到Port A的时钟连接必须是慢时钟,而连接到Port B的时钟必须是快时钟。 |
When you select With one read port and one write port, the following option is available: Create a ‘rden’ read enable signal |
— | 指定是否对端口B创建一个读使能信号。 |
When you select With two read/write ports, the following option is available: Create a ‘rden_a’ and ‘rden_b’ read enable signals |
指定是否对端口A和B创建一个读使能信号。 | |
Create byte enable for port A | — | 指定是否对端口A和B创建字节使能。如果要屏蔽输入数据,以便仅写入特定的字节,半字节或数据位,那么要打开这些选项。 要对端口A和端口B使能byte enable,RAM: 1-PORT和RAM: 2-PORT Intel® FPGA IP cores的数据宽度比必须为1或2。 对端口B创建字节使能的选项仅在选择了With two read/write ports选项时可用。 |
Create byte enable for port B | — | |
What is the width of a byte for byte enables? |
|
指定字节使能的一个字节的宽度。 此选项只有在选择了Create byte enable for port A和/或Create byte enable for port B时才可用。 |
Enable Error Correction Check (ECC) | On/Off | 指定是否使能ECC功能来纠正存储器输出上的单个位错误,两个相邻位错误和三个相邻位错误。 |
Enable ECC Pipeline Registers | On/Off | 指定是否在输出解码器之前使能ECC Pipeline Registers以达到与non-ECC模式相同的性能,但要以一个周期的延迟为代价。 |
Enable ECC Encoder Bypass | On/Off | 指定是否使能ECC编码器旁路功能,该功能使您能够通过eccencparity端口选择性地将奇偶校验位插入到存储器中。 |
Enable Coherent Read | On/Off | 指定是否使能一致性读取(coherent read)功能,此功能使您能够读出当前存储器内容,并对此内容执行操作,并在相同周期内写回到同一位置。 |
Parameter Settings: Regs/Clkens/Aclrs | ||
Which ports should be registered? When you select With one read port and one write port, the following options are available:
When you select With two read/write ports, the following options are available:
|
On/Off | 指定是否寄存读或写输入和输出端口。 |
Clock Enables When you select With one read port and one write port, the following option is available:
When you select With two read /write ports, the following options are available:
|
On/Off | 指定是否为读写寄存器创建时钟使能。
注: 对于MLAB模块,当选择Use clock enable for output registers选项时,可能会在第一个时钟周期产生非确定性输出。
|
Addressstalls When you select With one read port and one write port, the following option is available:
|
On/Off | 指定是否对地址寄存器创建时钟使能。您可以创建这些端口以用作地址寄存器的额外的低电平有效使能输入。 |
Aclr Options When you select With one read port and one write port, the following option is available:
When you select With two read /write ports, the following options are available:
|
On/Off | 指定是否为已寄存的端口创建异步清零端口。指定aclr端口是否清除‘q_a’和‘q_b’ 端口。 |
Sclr Options When you select With one read port and one write port, the following option is available:
When you select With two read /write ports, the following options are available:
|
On/Off | 指定是否对寄存端口创建一个同步清零端口。指定‘q_a’和‘q_b’端口是否被sclr端口清零。
注: 对于MLAB模块,当选择q_b port选项时,可能会在第一个时钟周期中产生非确定性输出。
|
Parameter Settings: Output 1 (此选项卡仅在选择了一个读端口和一个写端口时可用) | ||
How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port? |
|
指定read-during-write出现时的输出行为。
|
Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time. | On/Off | 当想要RAM对read-during-write操作输出‘don’t care’或者‘unknown’值而不进行时序路径分析时开启此选项。此选项仅用于LUTRAM,当存储器模块类型设置成MLAB时使能。 |
Parameter Settings: Output 2 (此选项卡仅在选择了两个读/写端口时可用) | ||
What should the ‘q_a’ output be when reading from a memory location being written to? |
|
指定read-during-write出现时的输出行为。
|
What should the ‘q_b’ output be when reading from a memory location being written to? | ||
Get x’s for write masked bytes instead of old data when byte enable is used | On/Off | 开启此选项以在屏蔽字节上获得‘X’。 |
Parameter Settings: Mem Init | ||
Do you want to specify the initial content of the memory? |
|
指定存储器的初始化内容。 如要将存储器初始化为零,则选择No, leave it blank。 如要使用存储器初始化文件(.mif)或者十六进制 (Intel-format)文件(.hex),则选择select Yes, use this file for the memory content data。 |
Initialize memory content data to XX..X on power-up in simulation | On/Off | — |
The initial content file should conform to which port's dimensions? | PORT_A, PORT_B | 如果您选择对存储器内容数据使用初始化内容文件,那么选择此文件应该符合的端口。 |
Implement clock-enable circuitry for use in a partial reconfiguration region | On/Off | 指定是否实现时钟使能电路以用于部分重配置区域。 |
Parameter Settings: Performance Optimization | ||
Enable Force to Zero | On/Off | 指定在置低读使能信号时是否将输出设成零。 当所选的存储器深度大于一个存储器模块时,使能此功能将有助于提高胶合逻辑性能。 |