Intel® Stratix® 10嵌入式存储器用户指南

ID 683423
日期 11/19/2019
Public
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4.3.15. FIFO Intel® FPGA IP参数

表 49.  FIFO Intel® FPGA IP参数说明此表列出了FIFO Intel® FPGA IP core的参数。
参数 合法值 说明
Parameter Settings: Width, Clk, Synchronization
How wide should the FIFO be? 指定数据和q端口的宽度。
How deep should the FIFO be? Note: You could enter arbritary values for width 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072 指定FIFO的深度(2的幂)。
Do you want a common clock for reading and writing the FIFO?
  • Yes, synchronize both reading and writing to 'clock'. Create one set of full/empty control signals.
  • No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for for each clock.
Parameter Settings: SCFIFO Options
Would you like to disable any circuitry protection?
  • full
  • empty
  • usedw[] (number of words in FIFO). Note: You can use the MSB to generate a half full flag.
  • almost full becomes true when usedw[] is greater than or equal to
  • almost empty becomes true when usedw[] is less than
  • Asyncronous clear
  • Syncronous clear (flush the FIFO)
On/Off
Parameter Settings: DCFIFO 1
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for for each clock., the following options are available:

Total latency, clock synchroniztion, metastability protection, area, and fmax options must be set as a group. Total latecny is the sum of two write clock rising edges and the number of read clocks selected below.

Which option(s) is most important to the DCFIFO? (Read clk sync stages, metastability protection, area, fmax)

Which type of optimization do you want?

  • Lowest latency but requires synchronized clocks. 1 sync stage, no metastability protection, smallest size, good fmax.
  • Minimal setting for unsynchronized clocks. 2 sync stages, good metastability, medium size, good fmax.
  • Best metastability protection, best fmax, unsynchronized clocks. 3 or more sync stages, best metastability protection, largest size, best fmax.
On/Off 指定总延迟,时钟同步,亚稳态保护,区域和fmax。
  • Lowest latency but requires synchronized clocks—此选项使用一个无亚稳态保护的同步阶段。它使用最小的尺寸并提供良好的fMAX。如果读和写时钟是相关时钟,请选择此选项。
  • Minimal setting for unsynchronized clocks—此选项使用两个具有良好亚稳态保护的同步阶段。它使用中等尺寸并提供良好的fMAX
  • Best metastability protection, best fmax, unsynchronized clocks—此选项使用具有最好的亚稳态保护的三个或更多的同步阶段。它使用最大尺寸并提供最好的fMAX
更多选项 当选择Best metastability protection, best fmax, unsynchronized clock时,下面选项可用:
  • How many sync stages?
3, 4, 5, 6, 7, 8, 9 指定同步阶段的数量。
Timing Constraint
  • Generate SDC file and disable embedded timing constraint
On/Off 通过正确的时序约束生成一个SDC文件。嵌入式set_false_path assignment被禁用。新的时序约束包括set_net_delayset_max_skewset_min_delayset_max_delay。关于时序约束使用的详细信息,请参考用户指南。
Parameter Settings: DCFIFO 2
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for for each clock., the following options are available:

Which optional output control signals do you want?

usedw[] is the number of words in the FIFO.

On/Off  
Read-side
  • full
  • empty
  • usedw[]

注意:这些信号与'rdclk'同步。

 
Write-side
  • full
  • empty
  • usedw[]

注意:这些信号与'wrclk'同步。

 
更多选项
  • Add an extra MSB to usedw port(s). 注意:您可以使用MSB生成一个half-full flag。
  • Asynchronous clear
  • Add circuit to synchronize 'aclr' input with 'wrclk'
  • Add circuit to synchronize 'aclr' input with 'rdclk'
On/Off  
Parameter Settings: Rdreq Option, Blk Type
Which kind of read access do you want with the 'rdreq' signal?
  • Normal synchronous FIFO mode.
  • Show-ahead synchronous FIFO mode.
指定FIFO处于Legacy模式还是Show-ahead模式。
  • Normal synchronous FIFO mode—'rdreq'置位后,数据变为可用。'rdreq'用作读请求(read request)。
  • Show-ahead synchronous FIFO mode—'rdreq'置位前,数据变为可用。'rdreq'用作读确认(read acknowledge)。注意:此模式会遭受性能损失。
What should the memory block type be?
  • Auto
  • MLAB
  • M20K
  • M144K
指定存储器模块类型。可选择的存储器模块类型取决于您的目标器件。
Set the maximum block depth to: Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072 指定最大模块深度(以字为单位)。
Reduce RAM usage (decreases speed and increases number of Les). Available if data width is divisible by 9. On/Off  
Parameter Settings: Optimization, Circuitry Protection
Would you like to register the output to maximize performance but use more area?
  • Yes (best speed)
  • No (smallest area)
指定是否寄存RAM输出。
Implement FIFO storage with logic cells only, even if the device contains memory blocks. On/Off 指定是否仅使用逻辑单元来实现FIFO存储。
Would you like to disable any circuitry protection (overflow checking and underflow checking)?
If not required, overflow and underflow checking can be disabled to improve performance.
  • Disable overflow checking. Writing to a full FIFO will corrupt contents.
  • Disable underflow checking. Reading from an empty FIFO will corrupt contents
On/Off 指定是否对上溢禁用任何电路保护
Would you like to enable ECC?
  • Enable error checking and correcting (ECC)
On/Off 指定是否使能错误检查和纠正功能。