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2.1. Intel® Stratix® 10嵌入式存储器模块中的字节使能(Byte Enable)
2.2. 地址时钟使能支持
2.3. 异步清零和同步清零
2.4. 存储模块错误纠正编码支持
2.5. Force-to-Zero
2.6. Coherent(一致性)读存储器
2.7. 冻结逻辑(Freeze logic)
2.8. 真双端口双时钟仿真器
2.9. Intel® Stratix® 10支持的嵌入式存储器IP内核
2.10. Intel® Stratix® 10嵌入式存储器时钟模式
2.11. Intel® Stratix® 10嵌入式存储器配置
2.12. 读和写地址寄存器的初始值
4.3.1. 配置方法
4.3.2. 规范
4.3.3. FIFO功能时序要求
4.3.4. SCFIFO ALMOST_EMPTY功能时序
4.3.5. FIFO输出状态标记和延迟
4.3.6. FIFO亚稳性保护及相关选项
4.3.7. FIFO同步清零和异步清零影响
4.3.8. SCFIFO和DCFIFO Show-Ahead模式
4.3.9. 不同的输入和输出宽度
4.3.10. DCFIFO时序约束设置
4.3.11. 手动例化的编码实例
4.3.12. 设计实例
4.3.13. 时钟域交叉上的格雷码计数器传输(Gray-Code Counter Transfer at the Clock Domain Crossing)
4.3.14. 嵌入式存储器ECC功能指南
4.3.15. FIFO Intel® FPGA IP参数
4.3.16. 复位方案(reset scheme)
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Ixiasoft
4.3.15. FIFO Intel® FPGA IP参数
参数 | 合法值 | 说明 | ||
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Parameter Settings: Width, Clk, Synchronization | ||||
How wide should the FIFO be? | — | 指定数据和q端口的宽度。 | ||
How deep should the FIFO be? Note: You could enter arbritary values for width | 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072 | 指定FIFO的深度(2的幂)。 | ||
Do you want a common clock for reading and writing the FIFO? |
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— | ||
Parameter Settings: SCFIFO Options | ||||
Would you like to disable any circuitry protection?
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On/Off | — | ||
Parameter Settings: DCFIFO 1 | ||||
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for for each clock., the following options are available: Total latency, clock synchroniztion, metastability protection, area, and fmax options must be set as a group. Total latecny is the sum of two write clock rising edges and the number of read clocks selected below. Which option(s) is most important to the DCFIFO? (Read clk sync stages, metastability protection, area, fmax) Which type of optimization do you want?
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On/Off | 指定总延迟,时钟同步,亚稳态保护,区域和fmax。
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更多选项 | 当选择Best metastability protection, best fmax, unsynchronized clock时,下面选项可用:
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3, 4, 5, 6, 7, 8, 9 | 指定同步阶段的数量。 | |
Timing Constraint
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On/Off | 通过正确的时序约束生成一个SDC文件。嵌入式set_false_path assignment被禁用。新的时序约束包括set_net_delay,set_max_skew,set_min_delay和set_max_delay。关于时序约束使用的详细信息,请参考用户指南。 | ||
Parameter Settings: DCFIFO 2 | ||||
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for for each clock., the following options are available: Which optional output control signals do you want? usedw[] is the number of words in the FIFO. |
On/Off | |||
Read-side
注意:这些信号与'rdclk'同步。 |
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Write-side
注意:这些信号与'wrclk'同步。 |
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更多选项 |
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On/Off | ||
Parameter Settings: Rdreq Option, Blk Type | ||||
Which kind of read access do you want with the 'rdreq' signal? |
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指定FIFO处于Legacy模式还是Show-ahead模式。
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What should the memory block type be? |
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指定存储器模块类型。可选择的存储器模块类型取决于您的目标器件。 | ||
Set the maximum block depth to: | Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072 | 指定最大模块深度(以字为单位)。 | ||
Reduce RAM usage (decreases speed and increases number of Les). Available if data width is divisible by 9. | On/Off | |||
Parameter Settings: Optimization, Circuitry Protection | ||||
Would you like to register the output to maximize performance but use more area? |
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指定是否寄存RAM输出。 | ||
Implement FIFO storage with logic cells only, even if the device contains memory blocks. | On/Off | 指定是否仅使用逻辑单元来实现FIFO存储。 | ||
Would you like to disable any circuitry protection (overflow checking and underflow checking)?
If not required, overflow and underflow checking can be disabled to improve performance.
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On/Off | 指定是否对上溢禁用任何电路保护 | ||
Would you like to enable ECC?
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On/Off | 指定是否使能错误检查和纠正功能。 |