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Ixiasoft
1.4.1.1. 使用同步的存储器模块
1.4.1.2. 避免不受支持的复位和控制条件
1.4.1.3. 检查Read-During-Write行为
1.4.1.4. 控制RAM推断和实现
1.4.1.5. 具有旧数据Read-During-Write行为的单时钟同步RAM
1.4.1.6. 具有新数据Read-During-Write行为的单时钟同步RAM
1.4.1.7. 简单双端口,双时钟同步RAM
Verilog HDL,简单双端口,双时钟同步RAM
VHDL,简单双端口,双时钟同步RAM
1.4.1.8. 真双端口同步RAM
1.4.1.9. 混合宽度双端口RAM
1.4.1.10. 带Byte-Enable信号的RAM
1.4.1.11. 上电时指定初始存储器内容
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Ixiasoft
1.4.1.7. 简单双端口,双时钟同步RAM
采用双时钟设计时,综合工具无法准确地推断read-during-write行为,因为它取决于目标器件中两个时钟的时序。 因此,综合设计的read-during-write行为是未定义的,可能与您的原始HDL代码有所不同。
Verilog HDL,简单双端口,双时钟同步RAM
module simple_dual_port_ram_dual_clock
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr, write_addr,
input we, read_clock, write_clock,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge write_clock)
begin
// Write
if (we)
ram[write_addr] <= data;
end
always @ (posedge read_clock)
begin
// Read
q <= ram[read_addr];
end
endmodule
VHDL,简单双端口,双时钟同步RAM
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dual_clock_ram IS
PORT (
clock1, clock2: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to 31;
read_address: IN INTEGER RANGE 0 to 31;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END dual_clock_ram;
ARCHITECTURE rtl OF dual_clock_ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg : INTEGER RANGE 0 to 31;
BEGIN
PROCESS (clock1)
BEGIN
IF (rising_edge(clock1)) THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
END IF;
END PROCESS;
PROCESS (clock2)
BEGIN
IF (rising_edge(clock2)) THEN
q <= ram_block(read_address_reg);
read_address_reg <= read_address;
END IF;
END PROCESS;
END rtl;