仅对英特尔可见 — GUID: mwh1409958538845
Ixiasoft
1.4.3.3. 在Verilog HDL中例化PR控制模块和CRC模块
此代码示例在Verilog HDL中例化一个顶级工程Chip_Top中的PR控制模块:
module Chip_Top (
//User I/O signals (excluding PR related signals)
..
..
//PR interface & configuration signals
pr_request,
pr_ready,
pr_done,
crc_error,
dclk,
pr_data,
init_done
);
//user I/O signal declaration
..
..
//PR interface and configuration signals declaration
input pr_request;
output pr_ready;
output pr_done;
output crc_error;
input dclk;
input [15:0] pr_data;
output init_done
stratixv_prblock stratixv_prblock_inst
(
.clk (dclk),
.corectl (1'b0),
.prrequest(pr_request),
.data (pr_data),
.error (pr_error),
.ready (pr_ready),
.done (pr_done)
);
stratixv_crcblock stratixv_crcblock_inst
(
.clk (clk),
.shiftnld (1'b1),
.crcerror (crc_error)
);
endmodule
关于读取Error Message Register (EMR)的端口连接的详细信息,请参考以下应用笔记。