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Ixiasoft
1.4.3.2. 在VHDL中例化PR控制模块和CRC模块
此代码示例在VHDL中例化一个顶级工程Chip_Top中的PR控制模块：
entity Chip_Top is port (
--User I/O signals (excluding PR related signals)
..
..
);
end Chip_Top;
-- Following shows the architecture behavior of Chip_Top
m_pr : stratixv_prblock
port map(
clk => dclk,
corectl =>'0', --1 - when using PR from inside
--0 - for PR from pins; You must also enable
-- the appropriate option in
Intel®
Quartus® Prime settings
prrequest => pr_request,
data => pr_data,
error => pr_error,
ready => pr_ready,
done => pr_done
);
m_crc : stratixv_crcblock
port map(
shiftnld => '1', --If you want to read the EMR register when
clk => dummy_clk, --error occurrs, refer to AN539 for the
--connectivity forthis signal. If you only want
--to detect CRC errors, but plan to take no
--further action, you can tie the shiftnld
--signal to logical high.
crcerror => crc_error
); 关于读取Error Message Register (EMR)的端口连接的详细信息，请参考以下应用笔记。