仅对英特尔可见 — GUID： uef1488510931078
Ixiasoft
小数分频PLL规范
| 符号 | 参数 | 条件 | Min | Typ | Max | 单位 |
|---|---|---|---|---|---|---|
| fIN | Input clock frequency | — | 30 | — | 800 49 | MHz |
| fINPFD | Input clock frequency to the phase frequency detector (PFD) | — | 30 | — | 700 | MHz |
| fCASC_INPFD | Input clock frequency to the PFD of destination cascade PLL | — | 30 | — | 60 | MHz |
| fVCO | PLL voltage-controlled oscillator (VCO) operating range | — | 6 | — | 12.5 | GHz |
| tEINDUTY | Input clock duty cycle | — | 45 | — | 55 | % |
| fOUT | Output frequency for internal global or regional clock | — | — | — | 644 | MHz |
| fDYCONFIGCLK | Dynamic configuration clock for reconfig_clk | — | — | — | 100 | MHz |
| tLOCK | Time required to lock from end-of-device configuration or deassertion of pll_powerdown | — | — | — | 1 | ms |
| tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
| fCLBW | PLL closed-loop bandwidth | — | 0.3 | — | 4 | MHz |
| tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | 50 | ps |
| tARESET | Minimum pulse width on the pll_powerdown signal | — | 10 | — | — | ns |
| tINCCJ 50 51 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.13 | UI (p-p) |
| FREF < 100 MHz | — | — | 650 | ps (p-p) | ||
| tOUTPJ 52 | Period jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
| FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
| tOUTCCJ 52 | Cycle-to-cycle jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
| FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
| dKBIT | Bit number of Delta Sigma Modulator (DSM) | — | — | 32 | — | bit |
相关信息
49 此规范受I/O最大频率的限制。取决于设计以及系统的具体因素，每个I/O标准可实现的最大I/O频率不同。确保设计中适当的时序收敛，并基于具体设计和系统设置执行HSPICE/IBIS仿真，以确定您系统中可达到的最大频率。
50 高输入抖动直接影响PLL输出抖动。要达到低PLL输出时钟抖动，您必须提供一个抖动< 120 ps的干净时钟源。
51 FREF为fIN/N，当 N = 1时，应用规范。
52 使用不同测量方法的外部存储器接口时钟输出抖动规范，可在 Intel® Cyclone® 10 GX器件的存储器输出时钟抖动规范列表中找到。