仅对英特尔可见 — GUID: mcn1413265701682
Ixiasoft
I/O PLL规范
符号 | 参数 | 条件 | 最小值 | 典型值 | 最大值 | 单位 |
---|---|---|---|---|---|---|
fIN | Input clock frequency | -1速度等级 | 10 | — | 800 62 | MHz |
-2速度等级 | 10 | — | 700 62 | MHz | ||
-3速度等级 | 10 | — | 650 62 | MHz | ||
fINPFD | Input clock frequency to the PFD | — | 10 | — | 325 | MHz |
fCASC_INPFD | Input clock frequency to the PFD of destination cascade PLL | — | 10 | — | 60 | MHz |
fVCO | PLL VCO operating range | -1速度等级 | 600 | — | 1600 | MHz |
-2速度等级 | 600 | — | 1434 | MHz | ||
-3速度等级 | 600 | — | 1250 | MHz | ||
fCLBW | PLL closed-loop bandwidth | — | 0.1 | — | 8 | MHz |
tEINDUTY | Input clock or external feedback clock input duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal global or regional clock (C counter) | –1,–2,–3速度等级 | — | — | 644 | MHz |
fOUT_EXT | Output frequency for external clock output | -1速度等级 | — | — | 800 | MHz |
-2速度等级 | — | — | 720 | MHz | ||
-3速度等级 | — | — | 650 | MHz | ||
tOUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | Non-SmartVID | 45 | 50 | 55 | % |
SmartVID | 42 | 50 | 58 | % | ||
tFCOMP | External feedback clock compensation time | — | — | — | 10 | ns |
fDYCONFIGCLK | Dynamic configuration clock for mgmt_clk and scanclk | — | — | — | 100 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of areset | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on the areset signal | — | 10 | — | — | ns |
tINCCJ 63 64 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.15 | UI (p-p) |
FREF < 100 MHz | — | — | 750 | ps (p-p) | ||
tOUTPJ_DC | Period jitter for dedicated clock output | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tOUTCCJ_DC | Cycle-to-cycle jitter for dedicated clock output | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tOUTPJ_IO 65 | Period jitter for clock output on the regular I/O | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ_IO 65 | Cycle-to-cycle jitter for clock output on the regular I/O | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tCASC_OUTPJ_DC | Period jitter for dedicated clock output in cascaded PLLs | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) |
相关信息
62 此规范受I/O最大频率限制。对于每种I/O标准,可达到的最大I/O频率是不同的,这取决于设计和系统的特定因素。要确保您设计中的时序收敛是正确的,并且要基于您的特定设计和系统设置来执行HSPICE/IBIS仿真,以决定您系统中可达到的最大频率。
63 高输入抖动直接影响PLL输出抖动。要达到低PLL输出时钟抖动,就必须提供一个低于120 ps的干净时钟源。
64 FREF等于fIN/N,当N = 1时应用规范。
65 外部存储器接口时钟输出抖动规范使用一个不同的测量方法,在 Arria® 10器件的存储器输出时钟抖动规范表中可以找到。