仅对英特尔可见 — GUID: mcn1398043965674
Ixiasoft
1.2.2.1.3. 仿真RSDS_E_1R发送器时序规范
符号 | 参数 | 模式 | –I6,–C7, –I7 | –A7 | –C8 | 单位 | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
最小 | 典型 | 最大 | 最小 | 典型 | 最大 | 最小 | 典型 | 最大 | ||||
fHSCLK | 输入时钟频率(高速I/O性能管脚) | x10 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz |
x8 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
x7 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
x4 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
x2 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
x1 | 5 | — | 170 | 5 | — | 170 | 5 | — | 170 | MHz | ||
HSIODR | 数据速率(高速I/O性能管脚) | x10 | 100 | — | 170 | 100 | — | 170 | 100 | — | 170 | Mbps |
x8 | 80 | — | 170 | 80 | — | 170 | 80 | — | 170 | Mbps | ||
x7 | 70 | — | 170 | 70 | — | 170 | 70 | — | 170 | Mbps | ||
x4 | 40 | — | 170 | 40 | — | 170 | 40 | — | 170 | Mbps | ||
x2 | 20 | — | 170 | 20 | — | 170 | 20 | — | 170 | Mbps | ||
x1 | 10 | — | 170 | 10 | — | 170 | 10 | — | 170 | Mbps | ||
fHSCLK | 输入时钟频率(低速I/O性能管脚) | x10 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz |
x8 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
x7 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
x4 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
x2 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
x1 | 5 | — | 170 | 5 | — | 170 | 5 | — | 170 | MHz | ||
HSIODR | 数据速率(低速I/O性能管脚) | x10 | 100 | — | 170 | 100 | — | 170 | 100 | — | 170 | Mbps |
x8 | 80 | — | 170 | 80 | — | 170 | 80 | — | 170 | Mbps | ||
x7 | 70 | — | 170 | 70 | — | 170 | 70 | — | 170 | Mbps | ||
x4 | 40 | — | 170 | 40 | — | 170 | 40 | — | 170 | Mbps | ||
x2 | 20 | — | 170 | 20 | — | 170 | 20 | — | 170 | Mbps | ||
x1 | 10 | — | 170 | 10 | — | 170 | 10 | — | 170 | Mbps | ||
tDUTY | 发送器输出时钟的占空比 | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS42 | 发送器通道到通道偏移 | — | — | — | 340 | — | — | 340 | — | — | 340 | ps |
tx Jitter | 输出抖动(用于多电源器件) | — | — | — | 500 | — | — | 500 | — | — | 500 | ps |
tRISE | 上升时间 | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | 下降时间 | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | PLL从器件配置结束进行锁定所需要的时间。 | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
42 TCCS规范仅适用于同一侧上的I/O bank。