仅对英特尔可见 — GUID: mwh1409958305118
Ixiasoft
4.11.1. 顶层Verilog HDL模块实例
顶层模块中的Verilog HDL ALTFP_MULT通过One Input连接Multiplexer。
module MF_top (a, b, sel, datab, clock, result); input [31:0] a, b, datab; input clock, sel; output [31:0] result; wire [31:0] wire_dataa; assign wire_dataa = (sel)? a : b; altfp_mult inst1 (.dataa(wire_dataa), .datab(datab), .clock(clock), .result(result)); defparam inst1.pipeline = 11, inst1.width_exp = 8, inst1.width_man = 23, inst1.exception_handling = "no"; endmodule