6.1. ALTMULT_ADD参数设置
有三组选项:General,Extra Modes和Multipliers。
GUI参数 | 参数 | 条件 | 值 | 说明 |
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What is the number of multipliers? | NUMBER_OF_MULTIPLIERS | — | 1,2,3或4 | 指定乘法器的数量,最多可以指定四个乘法器。 |
All multipliers have similar configurations | — | — | On或Off | 如果需要所有的乘法器有类似的配置,那么开启此选项。 |
How wide should the A input buses be? | WIDTH_A | — | 1–256 | 指定A输入总线的宽度。 |
How wide should the B input buses be? | WIDTH_B | — | 1–256 | 指定B输入总线的宽度。 |
How wide should the ‘result’ output bus be? | WIDTH_RESULT | — | 1–256 | 指定‘result’输出总线的宽度。 |
Create a 4th asynchronous clear input option | — | — | On或Off | 如果要创建第4个异步清零输入选项,那么开启此选项。 |
Create an associated clock enable for each clock | — | — | On或Off | 如果要对每个时钟创建一个关联时钟使能,那么开启此选项。 |
What is the representation format for A inputs? | REPRESENTATION_A | — |
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指定A输入的表示格式。 |
‘signa’ input controls the sign (1 signed/0 unsigned) | PORT_SIGNA | Input Representation > What is the representation format for A inputs? = Variable | More Options | 高电平‘signa’输入表示有符号,低电平‘signa’输入表示无符号。 |
Register ‘signa’ input | — | Input Representation > More Options | On或Off | 如果要使能 ‘signa’输入的寄存器,那么开启此选项。 |
Add an extra pipeline register | — | Input Representation > More Options | On或Off | 如果要使能额外的流水线寄存器,那么开启此选项。 |
Input Register > What is the source for clock input? | SIGNED_REGISTER_A | Input Representation > More Options | Clock0–Clock3 | 指定时钟输入源。 |
Input Register > What is the source for asynchronous clear input? | SIGNED_ACLR_A | Input Representation > More Options |
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指定异步清零输入源。 |
Pipeline Register > What is the source for clock input? | SIGNED_PIPELINE_REGISTER_A | Input Representation > More Options | Clock0–Clock3 | 指定时钟输入源。 |
Pipeline Register > What is the source for asynchronous clear input? | SIGNED_PIPELINE_ACLR_A | Input Representation > More Options |
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指定异步清零输入源。 |
What is the representation format for B inputs? | REPRESENTATIONS_B | — |
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指定B输入的表示格式。 |
‘signb’ input controls the sign (1 signed/0 unsigned) | PORT_SIGNB | Input Representation > What is the representation format for B inputs? = Variable | More Options | 高电平‘signb’输入表示有符号,低电平‘signb’输入表示无符号。 |
Register ‘signb’ input | — | Input Representation > More Options | On或Off | 如果要使能‘signb’输入的寄存器,那么开启此选项。 |
Add an extra pipeline register | — | Input Representation > More Options | On或Off | 如果要使能额外的流水线寄存器,那么开启此选项。 |
Input Register > What is the source for clock input? | SIGNED_REGISTER_B | Input Representation > More Options | Clock0–Clock3 | 指定时钟输入源。 |
Input Register > What is the source for asynchronous clear input? | SIGNED_ACLR_B | Input Representation > More Options |
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指定异步清零输入源。 |
Pipeline Register > What is the source for clock input? | SIGNED_PIPELINE_REGISTER_B | Input Representation > More Options | Clock0–Clock3 | 指定时钟输入源。 |
Pipeline Register > What is the source for asynchronous clear input? | SIGNED_PIPELINE_ACLR_B | Input Representation > More Options |
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指定异步清零输入源。 |
GUI参数 | 参数 | 条件 | 值 | 说明 |
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Create a shiftout output from A input of the last multiplier | — | — | On或Off | 开启以创建一个A输入的信号。 |
Create a shiftout output from B input of the last multiplier | — | — | On或Off | 开启以创建一个B输入的信号。 |
Register output of the adder unit | — | — | On或Off | 开启以创建加法器单元的寄存器输出。 |
What is the source for clock input? | OUTPUT_REGISTER |
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Clock0–Clock3 | 指定输出寄存器的时钟信号。 |
What is the source for asynchronous clear input? | OUTPUT_ACLR |
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指定异步清零输入源。 |
What operation should be performed on outputs of the first pair of multipliers? | MUTIPLIER1_DIRECTION | General > What is the number of multipliers? = 2, 3, or 4 |
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指定第二个加法器对和进行加还是减。值是加和减。如果选择变量,则使用addnsub1端口 |
‘addnsub1’ input controls the operation (1 add/0 sub) | — | Adder Operation > What operation should be performed on outputs of the first pair of multipliers? = Variable | More Options | 高‘addnsub1’输入表明加,低‘addnsub1’输入表明减。 |
Register ‘addnsub1' input | — | — | On或Off | 开启此选项以使能‘addnsub1’输入的寄存器 |
Add an extra pipeline register | — | — | On或Off | 如果要使能额外的流水线寄存器,那么开启此选项。 |
Input Register > What is the source for clock input? | ADDNSUB_MULTIPLIER_REGISTER[1] | Adder Operation > More Options | Clock0–Clock3 | 指定时钟输入源。 |
Input Register > What is the source for asynchronous clear input? | ADDSUB_MULTIPLIER_ACLR[1] | Adder Operation > More Options |
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指定异步清零输入源。 |
Pipeline Register > What is the source for clock input? | ADDNSUB_MULTIPLIER_PIPELINE_REGISTER[1] | Adder Operation > More Options | Clock0–Clock3 | 指定时钟输入源。 |
Pipeline Register > What is the source for asynchronous clear input? | ADDNSUB_MULTIPLIER_PIPELINE_ACLR[1] | Adder Operation > More Options |
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指定异步清零输入源。 |
What operation should be performed on outputs of the second pair of multipliers? | MUTIPLIER3_DIRECTION | General > What is the number of multipliers? = 4 | — | 指定第四个及后面所有奇数乘法器将其结果与和相加还是从和中减去。如果选择变量,则使用 addnsub3端口。 |
‘addnsub3’ input controls the sign (1 add/0 sub) - More Options | — | — | — | 高‘addnsub3’输入表明加,低‘addnsub3’输入表明减。 |
Register ‘addnsub3’ input | — | — | On或Off | 开启此选项以使能‘addnsub3’ 输入的寄存器。 |
Add an extra pipeline register | — | — | On或Off | 若要使能额外的流水线寄存器,则要开启此选项。 |
Input Register > What is the source for clock input? | ADDNSUB_MULTIPLIER_REGISTER[3] | Adder Operation > More Options | Clock0–Clock3 | 指定时钟输入源。 |
Input Register > What is the source for asynchronous clear input? | ADDSUB_MULTIPLIER_ACLR[3] | Adder Operation > More Options |
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指定异步清零输入源。 |
Pipeline Register > What is the source for clock input? | ADDNSUB_MULTIPLIER_PIPELINE_REGISTER[3] | Adder Operation > More Options | Clock0–Clock3 | 指定时钟输入源。 |
Pipeline Register > What is the source for asynchronous clear input? | ADDNSUB_MULTIPLIER_PIPELINE_ACLR[3] | Adder Operation > More Options |
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指定异步清零输入源。 |
Which multiplier-adder implementation should be used? | DEDICATED_MULTIPLIER_CIRCUITRY | — |
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指定乘法器加法器实现。 |
GUI参数 | 参数 | 条件 | 值 | 说明 |
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Register input A of the multiplier | — | — | On或Off | 开启以使能乘法器的寄存器输入A。 |
What is the source for clock input? | INPUT_REGISTER_A[0..3] |
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Clock0–Clock3 | 指定时钟输入源。 |
What is the source for asynchronous clear input? | INPUT_ACLR_A[0..3] |
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指定异步清零输入源。 |
Register input B of the multiplier | — | — | On或Off | 开启以使能乘法器的寄存器输入B。 |
What is the source for clock input? | INPUT_REGISTER_B[0..3] |
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Clock0–Clock3 | 指定时钟输入源。 |
What is the source for asynchronous clear input? | INPUT_ACLR_B[0..3] |
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指定异步清零输入源。 |
What is the input A of the multiplier connected to? | INPUT_SOURCE_A[0..3] | — |
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指定乘法器的输入A连接到multiplier input还是shiftin input。 |
What is the input B of the multiplier connected to? | INPUT_SOURCE_B[0..3] | — |
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指定乘法器的输入B连接到multiplier input还是shiftin input。 |
Register output of the multiplier | — | — | On或Off | 开启对乘法器的输出使能寄存器。 |
What is the source for clock input? | MULTIPLIER_REGISTER[] |
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Clock0–Clock3 | 指定时钟输入源。 |
What is the source for asynchronous clear input? | MULTIPLIER_ACLR[] |
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指定异步清零输入源。 |