仅对英特尔可见 — GUID： fxa1654228835885
Ixiasoft
3.8.1. 平台设计系统(Platform Design System)
| 信号 | 方向 | 宽度 | 说明 |
|---|---|---|---|
| cpu_clk_in_clk_clk | Input | 1 | CPU时钟。频率为100 Mhz。 |
| cpu_rst_in_reset_reset | Input | 1 | CPU复位 |
| redriver_i2c_master_sda_in | Input | 1 | 用于配置外部转接驱动器设置的I2C master接口。 |
| redriver_i2c_master_scl_in | Input | 1 | |
| redriver_i2c_master_sda_oe | Output | 1 | |
| redriver_i2c_master_scl_oe | Output | 1 | |
| txclk_i2c_master_sda_in | Input | 1 | I2C master接口，用于配置可编程振荡器，为没有视频帧缓冲器的RX-TX重发送设计输出TX视频时钟。 |
| txclk_i2c_master_scl_in | Input | 1 | |
| txclk_i2c_master_sda_oe | Output | 1 | |
| txclk_i2c_master_scl_oe | Output | 1 | |
| hdmi_rx_i2c_clk_clk | Input | 1 | DDC和SCDC接口的时钟输入。此时钟为100 Mhz。 |
| hdmi_rx_i2c_interface_scl | Input | 1 | HDMI RX DDC和SCDC接口 |
| hdmi_rx_i2c_interface_sda | Input | 1 | |
| hdmi_rx_hpd_interface_in_5v_power | Input | 1 | HDMI RX 5V检测和热插拔检测。请参考HDMI Intel FPGA IP User Guide中的Sink Interfaces部分来了解详细信息。 |
| hdmi_rx_hpd_interface_hpd | Output | 1 | |
| hdmi_rx_av_mm_aux_out_aux_pkt_data | Output | 72 | 辅助存储器接口。 请参考HDMI Intel FPGA IP User Guide中的Sink Interfaces部分来了解详细信息。 |
| hdmi_rx_av_mm_aux_out_aux_pkt_addr | Output | 7 | |
| hdmi_rx_av_mm_aux_out_aux_pkt_wr | Output | 1 | |
| hdmi_tx_hpd_interface_hpd | Input | 1 | HDMI TX热插拔检测接口 |
| hdmi_tx_i2c_interface_scl | Input | 1 | HDMI TX DDC和SCDC接口 |
| hdmi_tx_i2c_interface_sda | Input | 1 | |
| hdmi_tx_audio_interface_audio_mute | Input | 1 | HDMI TX音频静音控制。 0 = 音频取消静音 1 = 音频静音，忽略音频数据 |
| ddr4_emif_local_reset_req_local_reset_req | Input | 1 | DDR4的External Memory IP Interface (EMIF)。 请参考 英特尔Agilex 7 EMIF IP Interface and Signal Descriptions of External Memory Interface 英特尔Agilex 7 FPGA IP User Guide中的Section 4.1来了解详细信息。
注： 仅当选择了With Video Frame Buffer Design时才可用。
|
| ddr4_emif_local_reset_status_local_reset_done | Output | 1 | |
| ddr4_emif_pll_ref_clk_clk | Input | 1 | |
| ddr4_emif_oct_oct_rzqin | Input | 1 | |
| ddr4_emif_mem_mem_ck | Output | 1 | |
| ddr4_emif_mem_mem_ck_n | Output | 1 | |
| ddr4_emif_mem_mem_a | Output | 17 | |
| ddr4_emif_mem_mem_act_n | Output | 1 | |
| ddr4_emif_mem_mem_ba | Output | 2 | |
| ddr4_emif_mem_mem_bg | Output | 1 | |
| ddr4_emif_mem_mem_cke | Output | 1 | |
| ddr4_emif_mem_mem_cs_n | Output | 1 | |
| ddr4_emif_mem_mem_odt | Output | 1 | |
| ddr4_emif_mem_mem_reset_n | Output | 1 | |
| ddr4_emif_mem_mem_par | Output | 1 | |
| ddr4_emif_mem_mem_alert_n | Input | 1 | |
| ddr4_emif_mem_mem_dqs | Input | 9 | |
| ddr4_emif_mem_mem_dqs_n | Input | 9 | |
| ddr4_emif_mem_mem_dq | Input | 72 | |
| ddr4_emif_mem_mem_dbi_n | Input | 9 | |
| ddr4_emif_status_local_cal_success | Output | 1 | |
| ddr4_emif_status_local_cal_fail | Output | 1 | |
| dr_f_i_rst_n_reset_n | Input | 1 | Dynamic Reconfig IP接口 |
| dr_f_o_dr_curr_profile_id_o_dr_curr_profile_id | Output | 15 | |
| dr_f_o_dr_in_progress_o_dr_in_progress | Output | 1 | |
| dr_f_o_dr_error_status_o_dr_error_status | Output | 1 | |
| intel_hdmi_rx_phy_i2c_clk_clk | Input | 1 | HDMI RX收发器重新封装接口 |
| intel_hdmi_rx_phy_rx_serial_data_wire1 | Input | 4 | |
| intel_hdmi_rx_phy_rx_serial_data_n_wire1 | Input | 4 | |
| intel_hdmi_rx_phy_phy_interface_hdmi_5v_detect_n | Input | 1 | |
| intel_hdmi_rx_phy_phy_interface_rx_5v_detect | Output | 1 | |
| intel_hdmi_rx_phy_phy_interface_device_ready | Input | 1 | |
| intel_hdmi_tx_phy_tx_serial_data_wire1 | Output | 4 | HDMI TX收发器重新封装接口 |
| intel_hdmi_tx_phy_tx_serial_data_n_wire1 | Output | 4 | |
| intel_hdmi_tx_phy_tx_vid_clk_in_clk | Input | 1 | |
| intel_hdmi_tx_phy_phy_interface_device_ready | Input | 1 | |
| pll_vidclk_refclk_clk | Input | 1 | 视频时钟的IOPLL接口 |
| systemclk_f_out_systempll_synthlock_0_out_systempll_synthlock | Output | 1 | Transceiver SystemPLL时钟接口 |
| systemclk_f_refclk_fgt_in_refclk_fgt_0 | Input | 1 | |
| systemclk_f_refclk_fgt_in_refclk_fgt_1 | Input | 1 | |
| systemclk_f_refclk_fgt_in_refclk_fgt_2 | Input | 1 |