F-Tile动态重配置设计示例用户指南

ID 710582
日期 3/28/2022
Public
文档目录

1.5. 仿真设计示例测试台

步骤

请按照以下步骤对测试台进行仿真:

  1. 在命令提示符处,更改成测试台仿真目录 <design_example_dir>/example_testbench
    cd <my_design>/example_testbench
  2. 为您所选的仿真器运行仿真脚本。此脚本在仿真器中编译并运行测试台。请参考仿真测试台的步骤表。
  3. 分析结果。成功的仿真将显示“Testbench Passed”“Test Case Passed”消息。
    表 7.  在Synopsys VCS* Simulator中仿真测试台的步骤
    仿真器(Simulator) 说明
    VCS* 在命令行中输入:
    sh run_vcs.sh
    VCS* MX 在命令行中输入:
    sh run_vcsmx.sh
    Questa* 在命令行中输入:
    vsim -do run_vsim.do
    如果您想在不启动GUI的情况下进行仿真,则输入
    vsim -c -do run_vsim.do
    Xcelium* 在命令行中输入:
    sh run_xcelium.sh
    下面的示例输出显示了对CPRI多速率设计示例测试台进行了一次成功的仿真测试。
    NIOS is entering reset
    NIOS is exiting reset
    basic_avl_tb_top.cpriphy_dr_ed_hw__tiles.z1577a_x0_y0_n0.z1577a.z1577a_inst.PROTECTED: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.
    SIM Mode Conversion TX AM PERIOD Standard Mode: 163832 Sim Mode:   2552
    ** Info: Configuring ED to CPRI 10G ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 10G....
    ** Address offset = 0x1, WriteData = 0x00000001
    ** Address offset = 0x2, WriteData = 0x00008006
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 10G ....
    ** Address offset = 0x0, WriteData = 0x00000009
    ** Address offset = 0x1, WriteData = 0x00000009
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time             689130000
    Waiting for RX ready
    RX is ready is high at time             709850000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Info: Configuring ED to CPRI 9p8G ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 9p8G....
    ** Address offset = 0x1, WriteData = 0x00000006
    ** Address offset = 0x2, WriteData = 0x00008007
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 9p8G ....
    ** Address offset = 0x0, WriteData = 0x00000006
    ** Address offset = 0x1, WriteData = 0x00000006
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time            1561660000
    Waiting for RX ready
    RX is ready is high at time            1579800000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Info: Configuring ED to CPRI 4p9G ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 4p9G....
    ** Address offset = 0x1, WriteData = 0x00000007
    ** Address offset = 0x2, WriteData = 0x00008009
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 4p9G ....
    ** Address offset = 0x0, WriteData = 0x00000004
    ** Address offset = 0x1, WriteData = 0x00000004
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time            2415120000
    Waiting for RX ready
    RX is ready is high at time            2433780000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Info: Configuring ED to CPRI 2p4G ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 2p4G....
    ** Address offset = 0x1, WriteData = 0x00000009
    ** Address offset = 0x2, WriteData = 0x0000800b
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 2p4G ....
    ** Address offset = 0x0, WriteData = 0x00000002
    ** Address offset = 0x1, WriteData = 0x00000002
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time            3269140000
    Waiting for RX ready
    RX is ready is high at time            3287790000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Info: Configuring ED to CPRI 24p3G_RSFEC ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 24p3G_RSFEC....
    ** Address offset = 0x1, WriteData = 0x0000000b
    ** Address offset = 0x2, WriteData = 0x00008001
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 24p3G_RSFEC ....
    ** Address offset = 0x0, WriteData = 0x0000001b
    ** Address offset = 0x1, WriteData = 0x0000001b
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time            4158420000
    Waiting for RX ready
    RX is ready is high at time            4196310000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Testbench Completed
    ** Testbench Passed
    $finish called from file "basic_avl_tb_top.sv", line 452.
    $finish at simulation time 4196335ns
    
    下面的示例输出显示了对100G-4 Ethernet多速率动态重配置IP core variant进行了一次成功的仿真测试。
    ---SRC IP sequence TX ch0 completed ----
    ---SRC IP sequence TX ch1 completed ----
    
    ---SRC IP sequence RX ch0 completed ----
    ---SRC IP sequence RX ch1 completed ----
    
    ---Test 50G ch 0;   ---Total 16 packets to send ----
    Clearing counters
    -----Start 50G pkt gen TX ----
    -----Checking 50G Packet TX/RX result ----
    ---------- 16 packets Sent; 0 packets Received ----
    ------ALL 16 packets Sent out ---
    
    ---------- 16 packets Sent; 16 packets Received ----
    ------ALL 16 packets Received ---
    ------50G TX/RX packet check OK ---
    
    ---Test 50G ch 1;   ---Total 32 packets to send ----
    Clearing counters
    -----Start 50G pkt gen TX ----
    -----Checking 50G Packet TX/RX result ----
    ---------- 16 packets Sent; 0 packets Received ----
    ---------- 32 packets Sent; 32 packets Received ----
    ------ALL 32 packets Sent out ---
    ------ALL 32 packets Received ---
    ------50G TX/RX packet check OK ---
    
    *******************************************
    ** Testbench complete
    ** Testbench Passed
    **
    *******************************************
    下面的示例输出显示了对50G-1 PMA/FEC Direct PHY Multirate设计示例测试台进行了一次成功的仿真测试。
    ** Info: DONE Reconfigure to PMA DIR 50G ....
    ####### tx_reset, rx_reset deasserted ######
    1.08923e+09
    The time now is 1090000ns 
    
    The time now is 1100000ns 
    
    @1106614ns: TX Ready=0, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =0, cdr_lockedtoref =1, cdr_locktodata= 0, fnl_xcvr_locked_dut = 0,  tx_clkout_freq_valid=0, rx_clkout_freq_valid=0
    The time now is 1110000ns 
    
    @1110766ns: TX Ready=0, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 0, fnl_xcvr_locked_dut = 0,  tx_clkout_freq_valid=0, rx_clkout_freq_valid=0
    The time now is 1120000ns 
    
    @1126396ns: TX Ready=1, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 0, fnl_xcvr_locked_dut = 0,  tx_clkout_freq_valid=0, rx_clkout_freq_valid=0
    @1127420ns: TX Ready=1, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 0, fnl_xcvr_locked_dut = 0,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=0
    @1128074ns: TX Ready=1, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 1, fnl_xcvr_locked_dut = 1,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=0
    The time now is 1130000ns 
    
    The time now is 1140000ns 
    
    @1144500ns: TX Ready=1, RX Ready=1, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 1, fnl_xcvr_locked_dut = 1,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=0
    @1144815ns: TX Ready=1, RX Ready=1, verifier_error=0, verifier_lock =1, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 1, fnl_xcvr_locked_dut = 1,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=0
    @1145521ns: TX Ready=1, RX Ready=1, verifier_error=0, verifier_lock =1, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 1, fnl_xcvr_locked_dut = 1,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=1
    test_pass asserted at 1148815ns
    
    Test case passed
    Overall DR test passed
    Simulation passed