F-Tile动态重配置设计示例用户指南

ID 710582
日期 3/28/2022
Public
文档目录

1.7. 测试硬件设计示例

在编译F-Tile动态重配置设计示例并在 Intel® Agilex™ 器件上对其下载之后,可以使用System Console对IP core和它的PHY IP core寄存器进行配置。

请按照以下步骤启动System Console并测试硬件设计示例:

  1. Intel® Agilex™ 器件上加载硬件设计示例之后,在 Intel® Quartus® Prime Pro Edition软件中,点击Tools > System Debugging Tools > System Console
  2. 在Tcl Console窗格中,输入cd hwtest将目录更改为<design_example_dir>/hardware_test_design/hwtest
  3. 输入source main_script.tcl来打开与JTAG master的一个链接,然后开始测试。
  4. 分析结果。成功的运行将在System Console中显示Test Passed
    CPRI Multirate设计的样例输出:
    Info: Number of Channels = 1
    Info: JTAG Port ID       = 1
    Info: Power Up Variant   = 24G_RSFEC
    Info: Start of ftile_dr_cpri_test
    
    Info: Basic CPRI DR test
    
    	INFO: Checking PLL lock status...
    	iopll_sclk_locked 1
    	INFO: IOPLL sclk is locked
    	INFO: Set Reconfig Reset
    	INFO: Release Reconfig Reset
    Loop 0
    	INFO: Set RT Counter
    	INFO: Channel 0: Set TX Reset
    	INFO: Channel 0 : Checking tx reset ack n status...
    	INFO: TX fully in reset state 
    	INFO: Channel 0: Set RX Reset
    	INFO: Channel 0 : Checking rx reset ack n status...
    	INFO: RX fully in reset state 
    	Info: Channel: 0 Configuring ED to CPRI 10G ....
    	Info: Wait for DR Ready....
    	Info: Trigger DR interrupt
    	Info: Wait for DR interrupt Ack....
    		Info: DR Request acknowledged
    	Info: Wait for DR Config to be done....
    		Info: DONE Reconfigure to 10G.
    	INFO: Channel 0: Configuring cpri_speed
    	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 10G ....
    	INFO: Channel 0: Release TX Reset
    	Info: Check TX Ready Attempt: 1
    	INFO: Channel 0 : Checking TX ready status...
    		Info: tx_ready = 1
    	INFO: Channel 0: Release RX Reset
    	Info: Check RX Ready Attempt: 1
    	INFO: Channel 0 : Checking RX ready status...
    		Info: rx_ready = 1
    	INFO: Channel 0 : Checking RX PCS ready status...
    		Info: rx_pcs_ready  = 1
    	Info:Info: Channel: 0 Configuring DL ....
    	Info Channel: 0 sending packets in progress, waiting for checker pass ***
    	Info Channel: 0 waiting for measure_valid to assert...
    	INFO: Channel 0 : Checking hyperframe sync status...
    	INFO: hyperframe sync asserted
    	INFO: Channel 0 : Checking RT count done status...
    	INFO: RT count done asserted
    	Channel 0 : Read Determenistic latency counts
    	Channel 0 : Get checker_pass status:
    	Checker value = 1
    	Checker status = Passed!
    
    **
    *****************************************
    
    	INFO: Channel 0: Set TX Reset
    	INFO: Channel 0 : Checking tx reset ack n status...
    	INFO: TX fully in reset state 
    	INFO: Channel 0: Set RX Reset
    	INFO: Channel 0 : Checking rx reset ack n status...
    	INFO: RX fully in reset state 
    	Info: Channel: 0 Configuring ED to CPRI 9P8G ....
    	Info: Wait for DR Ready....
    	Info: Trigger DR interrupt
    	Info: Wait for DR interrupt Ack....
    		Info: DR Request acknowledged
    	Info: Wait for DR Config to be done....
    		Info: DONE Reconfigure to 9P8G.
    	INFO: Channel 0: Configuring cpri_speed
    	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 9P8G ....
    	INFO: Channel 0: Release TX Reset
    	Info: Check TX Ready Attempt: 1
    	INFO: Channel 0 : Checking TX ready status...
    		Info: tx_ready = 1
    	INFO: Channel 0: Release RX Reset
    	Info: Check RX Ready Attempt: 1
    	INFO: Channel 0 : Checking RX ready status...
    		Info: rx_ready = 1
    	Info:Info: Channel: 0 Configuring DL ....
    	Info Channel: 0 sending packets in progress, waiting for checker pass ***
    	Info Channel: 0 waiting for measure_valid to assert...
    	INFO: Channel 0 : Checking hyperframe sync status...
    	INFO: hyperframe sync asserted
    	INFO: Channel 0 : Checking RT count done status...
    	INFO: RT count done asserted
    	Channel 0 : Read Determenistic latency counts
    	Channel 0 : Get checker_pass status:
    	Checker value = 1
    	Checker status = Passed!
    
    **
    *****************************************
    
    	INFO: Channel 0: Set TX Reset
    	INFO: Channel 0 : Checking tx reset ack n status...
    	INFO: TX fully in reset state 
    	INFO: Channel 0: Set RX Reset
    	INFO: Channel 0 : Checking rx reset ack n status...
    	INFO: RX fully in reset state 
    	Info: Channel: 0 Configuring ED to CPRI 4P9G ....
    	Info: Wait for DR Ready....
    	Info: Trigger DR interrupt
    	Info: Wait for DR interrupt Ack....
    		Info: DR Request acknowledged
    	Info: Wait for DR Config to be done....
    		Info: DONE Reconfigure to 4P9G.
    	INFO: Channel 0: Configuring cpri_speed
    	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 4P9G ....
    	INFO: Channel 0: Release TX Reset
    	Info: Check TX Ready Attempt: 1
    	INFO: Channel 0 : Checking TX ready status...
    		Info: tx_ready = 1
    	INFO: Channel 0: Release RX Reset
    	Info: Check RX Ready Attempt: 1
    	INFO: Channel 0 : Checking RX ready status...
    		Info: rx_ready = 1
    	Info:Info: Channel: 0 Configuring DL ....
    	Info Channel: 0 sending packets in progress, waiting for checker pass ***
    	Info Channel: 0 waiting for measure_valid to assert...
    	INFO: Channel 0 : Checking hyperframe sync status...
    	INFO: hyperframe sync asserted
    	INFO: Channel 0 : Checking RT count done status...
    	INFO: RT count done asserted
    	Channel 0 : Read Determenistic latency counts
    	Channel 0 : Get checker_pass status:
    	Checker value = 1
    	Checker status = Passed!
    
    **
    *****************************************
    
    	INFO: Channel 0: Set TX Reset
    	INFO: Channel 0 : Checking tx reset ack n status...
    	INFO: TX fully in reset state 
    	INFO: Channel 0: Set RX Reset
    	INFO: Channel 0 : Checking rx reset ack n status...
    	INFO: RX fully in reset state 
    	Info: Channel: 0 Configuring ED to CPRI 2P4G ....
    	Info: Wait for DR Ready....
    	Info: Trigger DR interrupt
    	Info: Wait for DR interrupt Ack....
    		Info: DR Request acknowledged
    	Info: Wait for DR Config to be done....
    		Info: DONE Reconfigure to 2P4G.
    	INFO: Channel 0: Configuring cpri_speed
    	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 2P4G ....
    	INFO: Channel 0: Release TX Reset
    	Info: Check TX Ready Attempt: 1
    	INFO: Channel 0 : Checking TX ready status...
    		Info: tx_ready = 1
    	INFO: Channel 0: Release RX Reset
    	Info: Check RX Ready Attempt: 1
    	INFO: Channel 0 : Checking RX ready status...
    		Info: rx_ready = 1
    	Info:Info: Channel: 0 Configuring DL ....
    	Info Channel: 0 sending packets in progress, waiting for checker pass ***
    	Info Channel: 0 waiting for measure_valid to assert...
    	INFO: Channel 0 : Checking hyperframe sync status...
    	INFO: hyperframe sync asserted
    	INFO: Channel 0 : Checking RT count done status...
    	INFO: RT count done asserted
    	Channel 0 : Read Determenistic latency counts
    	Channel 0 : Get checker_pass status:
    	Checker value = 1
    	Checker status = Passed!
    
    **
    *****************************************
    
    	INFO: Channel 0: Set TX Reset
    	INFO: Channel 0 : Checking tx reset ack n status...
    	INFO: TX fully in reset state 
    	INFO: Channel 0: Set RX Reset
    	INFO: Channel 0 : Checking rx reset ack n status...
    	INFO: RX fully in reset state 
    	Info: Channel: 0 Configuring ED to CPRI 24G_RSFEC ....
    	Info: Wait for DR Ready....
    	Info: Trigger DR interrupt
    	Info: Wait for DR interrupt Ack....
    		Info: DR Request acknowledged
    	Info: Wait for DR Config to be done....
    		Info: DONE Reconfigure to 24G_RSFEC.
    	INFO: Channel 0: Configuring cpri_speed
    	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 24G_RSFEC ....
    	INFO: Channel 0: Release TX Reset
    	Info: Check TX Ready Attempt: 1
    	INFO: Channel 0 : Checking TX ready status...
    		Info: tx_ready = 1
    	INFO: Channel 0: Release RX Reset
    	Info: Check RX Ready Attempt: 1
    	INFO: Channel 0 : Checking RX ready status...
    		Info: rx_ready = 1
    	INFO: Channel 0 : Checking RX PCS ready status...
    		Info: rx_pcs_ready  = 1
    	Info:Info: Channel: 0 Configuring DL ....
    	Info:Info: Channel: 0 Programing RSFEC WA into DL counter ....
    	Info:Info: Channel: 0 Starting DL ....
    	Info Channel: 0 sending packets in progress, waiting for checker pass ***
    	Info Channel: 0 waiting for measure_valid to assert...
    	INFO: Channel 0 : Checking hyperframe sync status...
    	INFO: hyperframe sync asserted
    	INFO: Channel 0 : Checking RT count done status...
    	INFO: RT count done asserted
    	Channel 0 : Read Determenistic latency counts
    	Channel 0 : Get checker_pass status:
    	Checker value = 0
    	Checker status = Passed!
    
    **
    *****************************************
    
    Info: End of ftile_cpri_dr_test
    Info: Test <ftile_cpri_dr_test> Passed