基本要素

产品集
MAX® V CPLD
状态
Launched
发行日期
2010
光刻
180 nm

资源

逻辑元素 (LE)
2210
Equivalent Macrocells
1700
Pin-to-pin Delay
7 ns
User Flash Memory
8 Kb
Logic Convertible To Memory

特性

Internal Oscillator
Fast Power-on Reset
Boundary-scan JTAG
JTAG ISP
Fast Input Registers
Programmable Register Power-up
JTAG Translator
Real-time ISP
MultiVolt I/Os†
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5.0 V
I/O Power Banks
4
Maximum Output Enables
271
LVTTL/LVCMOS
Emulated LVDS Outputs
32 bit, 66 MHz PCI Compliant
1
Schmitt Triggers
Programmable Slew Rate
Programmable Pull-up Resistors
Programmable GND Pins
Open-drain Outputs
Bus Hold

封装规格

封装选项
F256, F324
封装大小
17mm x 17mm, 19mm x 19mm

补充信息

其他信息 URL