基本要素

产品集
MAX® V CPLD
状态
Launched
发行日期
2010
光刻
180 nm

资源

逻辑元素 (LE)
160
Equivalent Macrocells
128
Pin-to-pin Delay
7.5 ns
User Flash Memory
8 Kb
Logic Convertible To Memory

特性

Internal Oscillator
Fast Power-on Reset
Boundary-scan JTAG
JTAG ISP
Fast Input Registers
Programmable Register Power-up
JTAG Translator
Real-time ISP
MultiVolt I/Os†
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V
I/O Power Banks
2
Maximum Output Enables
79
LVTTL/LVCMOS
Emulated LVDS Outputs
Schmitt Triggers
Programmable Slew Rate
Programmable Pull-up Resistors
Programmable GND Pins
Open-drain Outputs
Bus Hold

封装规格

封装选项
M68, M100, E64, T100
封装大小
5mm x 5mm, 6mm x 6mm, 9mm x 9mm, 16mm x 16mm

补充信息

其他信息 URL