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Chevin Technology 的 10 G/25 G TCP/IP 卸载引擎是一种 FPGA 可合成以太网 TCP/IP 服务器/客户端,采用精简、快速的完整 RTL 解决方案。TCP/IP 卸载引擎提供了一种快速途径来创建启用 TCP 的应用程序,并在 FPGA 端使用最少的其他资源进行网络管理。AXI4-Lite 主机接口允许控制用于连接和链路监控的 TCP 寄存器和统计数据,并且每个会话都可路由。TCP 卸载引擎具有高度可配置性,可优化数据交换、功耗和延迟。软件驱动程序让用户可以轻松管理功能,例如使用 DMA 向应用程序发送和接收数据(有助于实现更高级别的协议);控制路由并管理 TCP 到多个应用程序的负载平衡;并在 AXI4 Streaming 和 AXI4 MM 之间动态切换。通过从内存存储数据和流,AXI4 Streaming 和内存接口可将功耗至多降低 2/3,并降低延迟和复杂性。符合 AXI4-Stream 标准的用户界面提供流量控制、会话识别和路由功能,可与系统开发和生产力工具(例如,英特尔® Quartus® 软件/英特尔® Platform Designer 等)无缝集成。
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ChevinID™ was designed by Chevin Technology using patented method (GB2609026) to add a further layer of protection to your Silicon supply chain by identifying malicious and accidental changes that can occur during the production process. ChevinID ™ authorizes and authenticates hardware and software functions, and establishes a secure root of trust, while allowing the selection, control and modification of features contained within encrypted envelopes of RTL netlists. ChevinID™ can be inserted into Silicon such as FPGA, ASIC, and SiP design with Chiplets.
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Chevin Technology’s HMAC-SHA256 cryptographic accelerator function is used to securely generate and verify message authentication codes. Message authentication is increasingly required by corporations, government organizations, and individuals to secure communications between sender and receiver. The HMAC – SHA256 authentication function is especially suited for cybersecurity, defense, and aerospace applications, and can be added to existing products, or designed into prototypes. Contact us for more information, or to discuss source code and netlist licensing options for Intel® FPGAs and ASICs.
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The TCP/IP (Transmission Control Protocol/ Internet Protocol) is an Ethernet IP stack for FPGAs that incorporates both the transport and internet layer protocols to deliver reliable, end to end network communications using the internet or on private networks. The TCP/ IP stack can be used with Chevin Technology’s 10G & 25G Ethernet IP cores for dependable, low-latency connectivity in any FPGA using a minimum of FPGA resources. Chevin Technology’s TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. Chevin Technology’s TCP/IP offloads the TCP protocol using fast and efficient logic for checksum calculation. Valuable resources in your application are freed up by the TCP/IP which offloads the entire TCP stack onto FPGA logic. Using the FPGA to analyse packets instead of the CPU significantly increases data transfer time and consistently reduces jitter. The TCP/IP is easily integrated alongside other protocols to provide an easy path for the development of TCP enabled FPGA applications. Chevin Technology offer flexible licensing terms and engineering support packages to suit the requirements of each customer.
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The UDP Protocol is a transport layer that runs on top of the Internet Protocol (IP) Layer and is used for connections where high sustained throughput is a priority and some data loss is expected, such as with video and audio streaming. Chevin Technology’s 10G & 25G UDP Ethernet IP core for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming receipt. De-fragmentation is available as an option, so large UDP datagrams can be easily sent and received. The UDP IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality. Chevin Technology’s 10G &25G UDP Ethernet IP core is configurable for Intel® & other FPGAs and simplifies integration by handling the complete Ethernet frame assembly. Chevin Technology’s UDP IP core is a mature IP core with proven success in customers’ projects. Reference designs are available for various boards to assist with integration and we offer our customers bespoke, expert engineering support packages to help meet their project goals. A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the user data payload is exchanged between the application and the UDP core. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi-port application is supported by a single UDP IP core by using the TDEST sideband embedded in the streaming interface.
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The IEEE 802.3by compliant 10/25G MAC/PCS was designed in house at Chevin Technology, to provide an easy path to the integration of protocols such as TCP/IP and UDP protocols in your FPGA, whilst using minimal FPGA resources. The 10/25GMAC simplifies the synthesis of ultra-fast Duplex 25Gbit/s Ethernet for FPGAs. The 10/25GMAC IP core is a Low-Latency Ethernet MAC with a latency of 44.8ns in 2749 LUTs for 10Gbit/s and 20.5ns in 2680 LUTs for 25Gbit/s. When combined with the Low-Latency 10/25GPCS, the full packet round trip time for 10Gbit/s is ( MAC Input -> Wire -> MAC Output ) 153.8ns in 5153 LUTs; 25Gbit/s ( MAC Input -> Wire -> MAC Output ) is 128ns in 7930 LUTs.Chevin Technology offer a detailed user guide, expert support and design services to assist in the implementation of 10/25Gbit/s Ethernet connectivity in Intel® Agilex™ and other FPGAs. A reference design is available for technology partner Bittware’s IA-840F and IA-420F boards, as well as Alpha Data’s ADM-PCIE-8V3, ADM-PCE-9V3 boards. Flexible licensing terms are available with Chevin Technology IP cores, to allow for the unique requirements of each customers’ project. We understand that efficiency and reliability are crucial to our customers, and have created a powerful CRC32 checker & generator engine that checks the TX and RX data for errors, on a 64bit wide bus @ 390.625MHz.Latency of the 10/25GMAC can be reduced even further by the use of Cut-through mode; the first byte appears only 8 nanoseconds after arriving at 25GMII. Alternatively, the Store-and-Forward mode reduces application workload, as the 25GMAC drops all corrupt frames. The Frame Checksum verifies frame integrity; the CRC32 check result is available 8 nanoseconds after the final byte is received. The Deficit Idle Count optimizes the Inter Frame Gap (IFG) for absolute maximum Throughput and minimum Latency by maintaining an average IFG count.