TotalHistory Embedded Logic Analyzer
关于此报价
TotalHistory IP Core for Signal Tracing Gidel’s Total History IP Core is an innovative signal tracing tool for FPGA prototyping enabling virtually unlimited signal trace depth, and massive and flexible probing of real system performance. TotalHistory uses the unused on-board memory and memory bandwidth of the FPGA boards, thus requires no additional resources. GiDEL’s novel TotalHistory IP opens the way to unprecedented design visibility. TotalHistory is based on a unique design-embedded IP core. Probes are inserted at any design point of interest to capture signals at full operating speed; signal trace is stored in the on-board memory or on peripheral SODIMMs at practically unlimited depth (up to 8.5 GB/FPGA) enabling virtually infinite signal tracing regression to accurately detect, reproduce, and isolate system bugs. Real-time signals are channeled to the host allowing user application processing to generate complex triggering schemes to detect bugs and to capture vital internal signal states. Once a trigger is issued, virtually infinite signal trace history can be retroactively analyzed by the host application, or by a simulator via the PCI/e bridge, or via Gigabit Ethernet (in the case of a PROC_SoCTM system). TotalHistory can support as much as 100,000 fully configurable probes per FPGA permitting comprehensive signal visibility. The TotalHistory IP provides an effective and simple means to probe and to debug complex FPGA designs.
详细信息
用例
工厂自动化
能源监控
视频管理
云计算 : 混合云
云计算 : 私有云
云计算 : 私有云和软件定义的基础架构
云计算 : 公有云
高级数据分析
库存管理
人工智能 : 图像/物体检测/识别/分类
人工智能 : 机器学习
人工智能 : 医疗成像
人工智能 : 视频监控和分析
工业
软件
Gidel
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Gidel
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Gidel 成立于 1993 年,持续为市场提供基于英特尔® FPGA 的硬件和软件产品。Gidel 产品针对各种市场(例如高性能计算 (HPC)、成像与视觉以及自动测试设备 (ATE))进行了优化。Gidel 的 COTS 硬件稳定、可靠、具有较长的生命周期,并获得了 ISO 9001-2008 质量认证。它提供满足最终用户系统要求的定制服务,这些系统由大型原始设备制造商 (OEM) 用于进行生产。Gidel 专门从事高性能采集和实时处理,一如既往地提供市场一流的成像和视觉性能。
Totalhistory Embedded Logic Analyzer
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