JESD204C
关于此报价
The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b66b encoding and includes full backwards compatibility with JESD204B and its 8b10b encoding. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
详细信息
覆盖区域
亚太地区和日本:
东南亚
澳大利亚和新西兰
亚洲其他地区
韩国
中国台湾地区
南亚地区
日本
欧洲、中东和非洲:
中欧地区
独立国家联合体
中东、土耳其和非洲
西欧联盟地区
中东欧
北欧联盟地区
南欧联盟地区
中华人民共和国:
中华人民共和国
美洲:
拉美地区
北美地区
用例
其它
工业
通信 : 数据处理
通信 : 出版(不包含网络出版)
通信 : 电信
航空航天和国防
其它
COMCORES
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COMCORES
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Comcores was founded in 2014 and is a key supplier of digital IP Cores and solutions with a focus on ethernet, wireless and chip-to-chip interfaces. We pride ourselves on providing the best-in-class, quality IP components and systems to ASIC, FPGA, and system vendors. Our core competence is the development and thorough validation of the IPs. By purchasing our IPs, we allow you to focus on your competences, drastically reducing your product cost, risk, and time to market.Our long-term background in mobile communication and being a first-mover in remote radio heads along with expertise in wireless networks gives us a solid foundation for understanding the complex requirements of modern communication tasks. This know-how coupled with 40+ dedicated coworkers/employees/professionals help us define and build state-of-the-art high-quality solutions.
Jesd204c
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