UDP/IP-1G: UDP/IP Hardware Protocol Stack
关于此报价
The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 1Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo Request and Reply Messages of the ICMP widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN. The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers. FEATURES: Complete UDP/IP Hardware Stack10/100/1000 Mbps Ethernet with a 31.25 MHz clock10Gbps Ethernet with a 312.5 MHz clock IPv4 support without packet fragmentation Jumbo and Super Jumbo Frames Transmit and Receive ARP with Cache ICMP (Ping Reply)IGMPv3 (Multicast)UDP/IP Unicast and Multicast UDP Port Filtering UDP/IP Checksums generation and validation, and optional Ethernet CRC validation VLAN (IEEE 802.1Q) support1 to 32 UDP transmit. and 1 to 32 UDP receive channels Ethernet Framing processing for non-UDP user-provided packets Optional DHCP client Trouble-Free Operation Run time programmable network parameters Local MAC address, Local IP address, Gateway IP address, and IP subnet mask Per-channel: Destination IP address, Source. and Destination UDP ports, multicast enable/disable and receive group ARP support for operation in networks with Dynamic IP allocation Easy SoC Integration Flexible interfaces: Packet Data: 32-bit streaming-capable Avalon-ST or AXI4-StreamControl/Status Registers: Generic 32-bit SRAM-like, or optionally 32-bit AHB, AXI, Avalon-MM or Wishbone Separate clock domains for packet processing and control/status interfaces Configurable buffer sizes Rich interrupt support for system events Optionally available pre-integrated with: Intel®, or other third-party eMAC core CAST Image and Video compression cores
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Udp/ip-1g: Udp/ip Hardware Protocol Stack
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