HSDLC: HDLC & SDLC Protocol Controller Core
关于此报价
Overview The HSDLC core is a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. The core operates as a peripheral to a host processor and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80c51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The controller’s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud-rate is programmable and limited only by the link drivers and the core’s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock. The HSDLC is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements triple-modular redundancy (TMR) to provide full immunity to single-bit upsets and errors and complies to Design Assurance, Level A (DAL-A) of the DO-254 standard.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 接口协议: 通信
- 最终客户类型:
-
中小企业
其它
企业
资源
采用的英特尔技术
Arria® V FPGA 和 SoC FPGA
英特尔® Stratix® 10 FPGA 和 SoC FPGA
英特尔® Cyclone® 10 FPGA
Cyclone® IV FPGA
英特尔® Agilex™ 7 FPGA 和 SoC FPGA
Cyclone® V FPGA 和 SoC FPGA
Stratix® IV FPGA
Stratix® V FPGA
英特尔® Arria® 10 FPGA 和 SoC FPGA
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Hsdlc: Hdlc & Sdlc Protocol Controller Core
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