H264-D-BP: Low-Latency AVC/H.264 Baseline Profile Decoder Core
关于此报价
The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the AVC/H.264 standard. It implements a hardware decoder with very low latency and high throughput that is suitable for live streaming and other delay-sensitive applications up to full HD resolution. The decoder adds just one macroblock line of latency, which means a negligible real-world latency under one msec for most widely used video formats, including HD/720p and Full-HD/1080p video. The H264-D-BP is designed for trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds with no assistance or input from the host processor. The decoder's memory interface is extremely flexible: it operates on a separate clock domain, is independent of the external memory type, and is tolerant to large latencies. The decoder reports decompressed video parameters, detects and reports bitstream errors to the system, and simplifies video cropping at its output.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: DSP: 视频和图像处理
- 最终客户类型:
-
中小企业
其它
企业
资源
采用的英特尔技术
英特尔® Stratix® 10 FPGA 和 SoC FPGA
英特尔® Arria® 10 FPGA 和 SoC FPGA
Stratix® V FPGA
英特尔® Agilex™ 7 FPGA 和 SoC FPGA
Arria® V FPGA 和 SoC FPGA
CAST
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H264-d-bp: Low-latency Avc/h.264 Baseline Profile Decoder Core
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