L8051XC1: Legacy-Configurable 8051-Compatible Microcontroller IP Core
关于此报价
The L8051XC1 core implements an MCS 51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU based systems. The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from various vendors. Several pre-configured versions are offered; custom variations are also available.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 处理器和外设: 嵌入式处理器
- 最终客户类型:
-
企业
资源
采用的英特尔技术
Cyclone® IV FPGA
Arria® V FPGA 和 SoC FPGA
Stratix® V FPGA
英特尔® MAX® 10 FPGA
Stratix® IV FPGA
Cyclone® V FPGA 和 SoC FPGA
英特尔® Arria® 10 FPGA 和 SoC FPGA
英特尔® Stratix® 10 FPGA 和 SoC FPGA
英特尔® Cyclone® 10 FPGA
英特尔® Agilex™ 7 FPGA 和 SoC FPGA
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L8051xc1: Legacy-configurable 8051-compatible Microcontroller Ip Core
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