英特尔® FPGA 原理图检查工作表

{"collectionRelationTags":{"relations":{"EXCLUDE":["etm-f6e0d09943a943d383e81b5f64a3956c","etm-ececc448f2f54f0e87cdf5558856b275"],"AND":["etm-DA5A91DF-5E20-493F-9B3E-14E037831DF1","etm-8f6fc0d61b3d4e57810103d6dc6bab78"]},"featuredIds":[]},"collectionId":"653175","resultPerPage":50.0,"filters":[{"facetId":"fpgadevicefamily","type":"fpgadevicefamily","deprecated":true,"name":"fpgadevicefamily","position":0},{"facetId":"lastupdated","type":"lastupdated","deprecated":true,"name":"lastupdated","position":1}],"coveoRequestHardLimit":"1000","accessDetailsPagePath":"/content/www/us/en/secure/design/internal/access-details.html","collectionGuids":["etm-DA5A91DF-5E20-493F-9B3E-14E037831DF1","etm-8f6fc0d61b3d4e57810103d6dc6bab78"],"cardView":false,"sorting":"Newest","defaultImagesPath":"/content/dam/www/public/us/en/images/uatable/default-icons","coveoMaxResults":5000,"fpgaFacetRootPaths":"{\"fpgadevicefamily\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Programmable Devices\"],\"quartusedition\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software\"],\"quartusaddon\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software - Add-ons\"],\"fpgaplatform\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® FPGA Platforms\"]}","newWrapperPageEnabled":true,"descendingSortingForNumericalFacetsName":"[\"Intel® Quartus® Prime Pro Edition\",\"Intel® Quartus® Prime Lite Edition\",\"Intel® Quartus® Prime Standard Edition\",\"Quartus® II Subscription Edition\",\"Quartus® II Web Edition\"]","columnsConfiguration":{"idColumn":true,"dateColumn":true,"versionColumn":true,"contentTypeColumn":false,"columnsMaxSize":0},"dynamicColumnsConfiguration":[{"name":"DynamicColumn_id","type":"id","gtv":"ID","width":60,"selected":true},{"name":"DynamicColumn_date","type":"date","gtv":"日期","width":60,"selected":true},{"name":"DynamicColumn_version","type":"version","gtv":"版本","width":135,"selected":true}],"updateCollateralMetadataEnabled":true}