With today's time-to-market constraints, you must plan your FPGA I/O pins early in the design cycle. Quartus® II software has best-in-class I/O management tools for early I/O planning and sign-off. While planning your I/O pins, prepare your FPGA design for PCB integration. Create "board-aware" board trace models in Quartus II software to get I/O signal integrity metrics or generate IBIS/HSPICE models for simulation in third-party signal integrity simulation tools. Export the I/O pin-outs to create custom schematic symbols for use in popular schematic capture tools.
For additional information on I/O management, PCBs, and board-level signal integrity, see the following:
- I/O Management Documentation
- I/O Management Training and Demonstrations
- I/O Navigator
- Design Examples
- Pin-Out Files for Altera® Devices
- Pin Connection Guidelines
- BSDL Files for Altera Devices
- PCB Design Documentation
- PCB Design Resource and Training
- Capture CIS Symbols
- Board-Level Signal Integrity Documentation
- Signal Integrity Analysis Training
- Signal Integrity Technology Center
For a brief overview of the I/O features in Quartus II software, refer to the Quartus II software features page.
For further technical support, use mySupport to create, view, and update your service requests.
I/O Management Resources
Table 1 provides links to available documentation on I/O management. For details on I/O features and supported standards of Altera FPGAs, refer to the selectable I/O standards chapter in the appropriate device handbook.