® An Introduction to the Intel QuickPath Interconnect

An Introduction to the Intel® QuickPath Interconnect

An Introduction to the Intel® QuickPath Interconnect, January 2009

Executive Overview

Intel® microprocessors advance their performance ascension through ongoing microarchitecture evolutions and multi-core proliferation. The processor interconnect has similarly evolved, thereby keeping pace with microprocessor needs through faster buses, quad-pumped buses, dual independent buses (DIB), dedicated high-speed interconnects (DHSI), and now the Intel® QuickPath Interconnect.

The Intel QuickPath Interconnect is a highspeed, packetized, point-to-point interconnect used in Intel’s next generation of microprocessors first produced in the second half of 2008. The narrow high-speed links stitch together processors in a distributed shared memory-style platform architecture. Compared with today’s wide front-side buses, it offers much higher bandwidth with low latency. The Intel QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems. It has a snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture to meet the needs of even the most mission-critical servers. With this compelling mix of performance and features, it’s evident that the Intel QuickPath Interconnect provides the foundation for future generations of Intel microprocessors and that various vendors are designing innovative products around this interconnect technology.

Read the full Introduction to the Intel® QuickPath Interconnect White Paper.