文章 ID: 000085861 内容类型: 故障排除 上次审核日期: 2021 年 08 月 28 日

Altera建议不要使用afi_half_clk

环境

    英特尔® Quartus® II 订阅版
BUILT IN - ARTICLE INTRO SECOND COMPONENT

关键问题

说明

此问题影响 DDR2 和 DDR3、LPDDR2、QDR II 和 RLDRAM II 产品。

以下警告消息可能会在 TimeQuest 中显示 运行 Report DDR 命令后的时序分析器。

在配备 DDR2、DDR3、LPDDR2、QDR II 的 Arria V 设备上, 或 RLDRAM II 接口:

Timing analysis was performed on core 内核名> using Quartus II v12.0 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing model.

在配备 LPDDR2、QDR II 或 RLDRAM II 的 Arria V 设备上 接口:

Core: 内核名> was generated using Quartus II v12.0 for Arria V. POF generation is not supported for this core in this release of Quartus II. You must regenerate this IP in a future version of Quartus II to obtain POF support..

在配备 DDR2、DDR3 或 LPDDR2 接口的 Cyclone V 设备上:

Core: 内核名 > was generated using Quartus II v12.0 for Cyclone V. POF generation is not supported for this core in this release of Quartus II. You must regenerate this IP in a future version of Quartus II to obtain POF support. Timing analysis was not performed on core 内核名 > because the Quartus II v12.0 software contains preliminary timing models for Cyclone V devices. You must regenerate this IP in a future version of Quartus II to update the timing model and constraints.

在 Stratix V 设备上配备 DDR2、DDR3、QDR II 或 RLDRAM II 接口:

Timing analysis was performed on core 内核名> using Quartus II v12.0 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing model.

解决方法

此问题的变通办法是不要使用 afi_half_clk

此问题将无法解决。

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