由于 PCI Express 英特尔® Arria® 10 硬核 IP 的时序限制问题,您可能会在时序分析器中遇到以下警告:
节点:<ip 实例>|altpcie_a10_hip_hwtcl:pcie_1x|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g1x1:g_xcvr.g_phy_g1x1.phy_g1x1|altera_xcvr_native_a10:phy_g1x1|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es2:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es2:inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_iinm_hssi_common_pcs_pma_interface~pma_hclk.reg 被确定为时钟,但未进行相关的时钟分配。
应用以下时序限制来正确约束此时钟:
create_generated_clock -name {pcie_1x|pma_hclk_by2} -source [get_pins -compatibility_mode {*altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g1g2x1.fpll_g1g2x1|fpll_g1g2x1|fpll_refclk_select_inst|refclk}] -duty_cycle 50.000 -multiply_by 5-divide_by 2 [get_pins -compatibility_mode {*altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g1x1.phy_g1x1|phy_g1x1|g_xcvr_native_insts[0]。twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_iinm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}]
这个问题将在 Quartus® II 软件的未来发行版中得到解决。