Introduction to the Triple-Speed Ethernet MegaCore Function (OTSE1116)

28 Minutes Online Course

Course Description

This online course will introduce you to the features and interfaces of the Triple-Speed Ethernet MegaCore Function targeting Altera® transceiver devices using the Quartus® II software.

At Course Completion

You will be able to:

  • Describe the features, functionality and interfaces of the TSE MegaCore IP function when using devices with embedded transceivers

Skills Required

  • Understanding of the Ethernet technology specifications
  • Familiarity with common high-speed transceiver architecture OR viewing the following course: Transceiver Basics
  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus II design software
  • Some familiarity with Qsys

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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