Are you targeting an Intel® Stratix® 10 FPGA and wanting to learn how your design can reach the maximum core performance?
This course will give you an introduction to advanced optimization techniques for the HyperFlex™ architecture found in Stratix 10 FPGAs. In this course, you will learn about design practices that limit the effectiveness of Hyper-Retiming and Hyper-Pipelining and about Hyper-Optimization techniques that can be used to to overcome those bottlenecks thus unleashing the full potential of the HyperFlex architecture.
At Course Completion
You will be able to:
- Understand factors that may reduce the effectiveness of Hyper-Retiming and Hyper-Pipelining
- Locate and evaluate loop structures that reduce design performance
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus® Prime Pro design software
- Familiarity with Verilog or VHDL synthesizable design structures
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
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