Course DescriptionIn this course, you will learn reset design techniques that you can use to achieve reliable power-up and reset release conditions along with maximum performance on Intel Hyperflex FPGA architecture devices.
The main purpose in providing a reset to your design is to provide stability and to prevent power-on to an unknown state. However, improper reset implementation can cause functional errors. Improper reset implementation can also cause restrictions during the Fitter’s Retime Stage. These restrictions can limit the register movement that balances propagation delays between registers in a chain to shorten critical paths and increase frequency of operation.
At Course Completion
You will be able to:
>You will be able to have a better understanding on the reset needs of your design and whether you will need to redesign your reset tree.
> Familiarity with Intel Quartus Prime Pro software
> Familiarity with HDL simulation
We recommend completing the following courses:
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: