Course DescriptionIn this training you will learn about the Hard Processor Subsystem (HPS) in the Cyclone® V, Arria® V, and Arria 10 SoC device. We will discuss the AMBA® AXI™ bridges, the Level 3 and Level 4 interconnects, and various types of memory that are included in the HPS.
At Course Completion
You will be able to:
- Understand the AMBA AXI bridge architecture
- Understand the Level 3 and Level 4 interconnect
- Understand the On-Chip RAM and Boot ROM
- Understand the features of the HPS SDRAM
- Basic knowledge of FPGA architecture