Clock Domain Crossing Considerations (ODSWCDCC)

19 Minutes Online Course

Course Description

This course presents some considerations when crossing clock domains in Intel® FPGAs. The course reviews metastability and synchronizer circuits, goes over the CDC Viewer reporting tool found in Intel Quartus® Pro Software Timing Analyzer, and uses a simple design to cross clock domains.

At Course Completion

You will be able to:

  • Use the CDC Viewer in Timing Analyzer
  • Analyze clock domain crossing designs
  • Constrain clock domain crossing designs

Skills Required

  • Familiarity with Intel Quartus Prime Pro software
  • Familiarity with Timing Analyzer

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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