Understanding Timing Analysis in FPGAs (ODSW1119)

30 Minutes Online Course

Course Description

Timing analysis is one of the most critical steps in the FPGA design flow. The Understanding Timing Analysis in FPGAs course is the first step in learning to use the Timing Analyzer as it introduces the many timing parameters and equations used in timing reports to describe FPGA performance. These include register parameters like setup, hold, recovery and removal, and their associated slack calculations. Understanding these parameters and calculations is key to timing closure, the process used by FPGA designers to fix a design that fails timing.

At Course Completion

You will be able to:

  • Describe the register timing parameters and why they are important in synchronous design
  • Describe the computations performed during timing analysis to ensure successful operation
  • Describe the effects of timing models on timing analysis

Skills Required

  • Background in digital logic design
  • Familiarity with FPGA/CPLD design flow

Prerequisites

We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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