Timing Analyzer: Introduction to Timing Analysis (ODSW1115)

15 Minutes Online Course

Course Description

This training is part 1 of 4. Closing timing can be one of the most difficult and time-consuming aspects of creating an FPGA design. The Timing Analyzer, part of the Intel® Quartus® Prime software, is an easy-to-use tool for creating Synopsys* design constraints (SDC) files and for generating detailed timing reports to shorten the process of timing closure. This part of the training introduces you to the basic timing analysis concepts required for understanding how to use the tool.

At Course Completion

You will be able to:

  • Learn basic timing analysis concepts required for using the Timing Analyzer tool
  • Understand the idea of the SDC netlist and its hierarchy for targeting timing constraints to points in a designNon

Skills Required

  • Background in digital logic design
  • An understanding of basic FPGA design flow
  • A solid working knowledge of the Intel Quartus Prime software

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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