Course DescriptionThis training is a recording of the “Debugging with Signal Tap in Intel FPGAs Office Hours” session held on 1/28/2021. Office Hours give you the opportunity to ask questions directly to an Intel FPGA expert and learn from others’ questions. In this Office Hours session, Intel FPGA Training Engineer Steven Strell answers questions about the implementation and use of the Signal Tap embedded logic analyzer debugging tool found in the Intel Quartus® Prime software.
At Course Completion
You will be able to:
> Aspects of the use of the Signal Tap logic analyzer based on user questions
> Basic understanding of the use of the Intel Quartus Prime software
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: