| Error nofile(37) in protected region |
| How do I download the latest version of the Board Skew Parameter Tool? |
| How do I decide when to compensate for the package delay mismatch (Package Deskew) when routing the board traces for my memory interface? |
| Intel® Stratix® 10 SX Device Features |
| Package effects when probing at the FPGA pin |
| Does Altera provide support for Multi-port Front End IP implemented in the core FPGA fabric? |
| Is there a guideline and checklist for debugging calibration failure |
| ERR_MaxRefsPostponed :: More than a total of 8 Refresh commands postponed by more then trefi = <trefi_value> ns |
| How do I implement the half rate bridge option for connection to a full rate memory controller ? |
| Critical Warning: PLL clock *|divclk not driven by a dedicated clock pin or neighboring PLL source. |
| Critical Warning: PLL clock *|divclk not driven by a dedicated clock pin or neighboring PLL source. |
| Does the UniPHY External Memory Interface IP support dynamic reconfiguration of it's parameters ? |
| What are the minimum memory clock frequencies supported by the UniPHY External Memory Interface IP ? |
| Internal Error: /JTAG/serial_flash_loader_0 () does not have a matching existing connection path |
| Why do I see long simulation times when simulating UniPHY-based controllers in skip calibration mode? |
| What is the afi_reset_export_n port used for? |
| Why is tREFI value in simulation and board measurement different from what is set in Altmemphy and UniPHY based DDR2 SDRAM memory controller? |
| Warning (15946): DQS_INPUT_FREQUENCY parameter of DQS delay chain should be equal to the INPUT_FREQUENCY parameter of DLL |
| WARNING: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is ‘x’ |
| Can the DDR3 mem_reset_n signal be controlled by a user-accessible register? |
| Error: Error during execution of script generate_ed.tcl: <example design>: Interface seq_debug tried to export unknown interface if0.seq_debug |
| The supplied JTAG Debug Information (.jdi) file for the project does not appear to match the specified target device as not all nodes have hierarchy info. |
| Why does the example design simulation fail when the UniPHY controller is generated with PHY only option? |
| Error (129036): Output port DATAOUT on atom "<slave DQS signal>", which is a arriav_delay_chain primitive, is not connected to a valid destination |
| * Error: Module parameter 'CFG_CMD_GEN_OUTPUT_REG' not found for override at alt_mem_ddrx_controller.v |
| Critical Warning: _p0_pin_map.tcl: Failed to find PLL clock for pins |
| Internal Error: io_obuf_iterm->is_inverted() == comp_obuf_iterm->is_inverted() |
| ** Warning nofile(37) in protected region. |
| Can the address pins be swapped on my DDR2 or DDR3 UniPHY controller? |
| How do I set the timing parameters for DDR3L? |
| Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of <block ID number> (<number of pins> locations affected) |
| Why does the EMIF toolkit generate a blank report when masking a rank? |
| Why does the example design for the UniPHY-based memory controller have an Avalon-MM slave port as top-level I/O? |
| Why do I see R105 warnings on the DDR3 reset paths when using the Design Assistant tool? |
| Why do I see bit errors with my DDR3 controller? |
| How do I reduce the UniPHY DDR3 controller pulsing avl_ready low on the Avalon interface? |
| What are the AC voltage levels that Quartus® II uses for UniPHY DDR3 and DDR3L tDS and tIS set up derating ? |
| ncelab: *E,USMSLC (../submodules/sequencer_scc_mgr.sv,321|24): Unsupported memory slice specification using part select or indexed part select. |
| Is there a way to control the latency between afi_rdata_en and afi_rdata_valid in the UniPHY-based memory controllers? |
| What are the local_cal_success and local_cal_fail signals of UniPHY-based memory controllers? |
| Error: Error during execution of "{C:/altera/12.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally |
| WARNING: Attempting to read from uninitialized location |
| How do you export the EMIF Toolkit full calibration and margin report in one file ? |
| Why do I get a no-fit when using the Altera External Memory Interface IP in an FPGA device that has a relatively low number of IO banks? |
| Why is my HPS DDR3 controller failing calibration? |
| Why does the Avalon interface of my DDR3 UniPHY-based memory controller use Avalon-MM signals instead of Avalon-ST signals? |
| Do the UniPHY-based memory controllers support Short ZQ Calibration? |
| Why does my project with a RLDRAM or QDR interface stall in the fitter? |
| What are the AC voltage levels that Quartus® II uses for DDR2 and LPDDR2 tDS and tIS set up derating ? |
| Why does the EMIF toolkit fail to recognize the memory interface when it is generated in Qsys? |
| Error: Could not find a location with: OCT_CAL_BLOCK_ID |
| Why is afi_rlat tied to ground in my UniPHY-based PHY-Only instance of the external memory interface? |
| Why is my Qsys UniPHY based memory controller missing the pin_assignments.tcl file and other support files? |
| Error : Illegal constraint of DLL to the region (X, Y) to (X, Y): no valid locations in region |
| How do I calculate the ECC for DDR3 UniPHY based controller? |
| Error: s0: Error during execution of "<Intel® Quartus Prime installation>/nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally |
| Why is tRCD larger than expected with my DDR3 UniPHY controller? |
| Why are the DDR3 controller write-to-read and read-write turnaround times longer than expected? |
| How do I remove the on-chip termination from my UniPHY-based memory controller? |
| Warning (332009): The launch and latch times for the relationship between source clock: and destination clock: are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. |
| Why do I observe read errors with my UniPHY based memory controller IP after migrating the IP to a different version of the Quartus II software? |
| Error (15700): Termination calibration block atom "&lt;variation name&gt;|altera_mem_if_oct_stratixv:oct0|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout |
| Error: Channel uncertainties must be greater than or equal to 0 |
| Could not find the TCP port for the System Console process within the elapsed time limit |
| Where can I find the ALTMEMPHY and UniPHY IP tutorials and example design projects that were previously covered in the External Memory Interface Handbook? |
| Why has the option "Enable read DQS tracking" in UniPHY based DDR3 SDRAM IP changed between Quartus II software releases? |
| Is it possible to retain data in a memory device during the UniPHY calibration process? |
| How config_data is shifted into the scan chain block when dynamic reconfiguration is used in ALTDQ_DQS2 Megafunction? |
| Why do the CSR registers report ECC data errors when the read data is not corrupted? |
| Why do I see random read errors when using the DDR2, DDR3/DDR3L and LPDDR2 UniPHY IP on the Arria V GX/GT/SX/ST and Cyclone V E/GX/GT/SE/SX/ST devices? |
| Error (175006): Could not find path between source global or regional clock driver and the HMC |
| Error: "933.333" is not a valid memory speed grade |
| Why is avl_ready stuck low in my DDR3 UniPHY-based controller in Quartus II 12.0SP2? |
| How do I fix the core setup timing violations when I bond two DDR3 hard memory controllers from the top edge to bottom edge of the FPGA device? |
| Why is the afi_half_clk signal not constrained in my UniPHY-based memory controller? |
| Can I implement single rank DDR2 SDRAM or DDR3 SDRAM DIMM/device for a design created for dual rank? |
| Is table below in Arria V and Cyclone V handbook DQ/DQS number for hard memory controller? |
| Does <instance_name>_pin_assignment.tcl script for DDR, DDR2 and DDR3 SDRAM High Performance controller I and II automatically find the memory pin name at top level design? |
| Are there any issues with the UniPHY IP Global Signal assignments seen in the Quartus II software Assignments editor after running the <variation_name>_pin_assignments.tcl script? |
| Why do I see random read errors using DDR2 SDRAM Controller with UniPHY/ DDR3 SDRAM Controller with UniPHY or LPDDR2 SDRAM Controller with UniPHY? |
| Why is the DDR3 HMC with multiple MPFE ports hanging in simulation with ModelSim |
| Why does the DDR3 hard memory controller with UniPHY return invalid read data after the individual multi-port front end port is reset? |
| How do I connect the signals of the ALTDQ_DQS2 Hard Read FIFO? |
| Can the PCIe Hard IP core and the DDR3 IP core share the same refclk? |
| Should I use the option "Generate power-of-2 data bus widths for Qsys or SOPC Builder" in DDR2 or DDR3 SDRAM Controller with UniPHY? |
| Why is the EMIF debug toolkit hanging in 12.0SP2? |
| Can I generate a hard memory controller without the hard MPFE? |
| Why the Maximum Avalon-MM burst length options in DDR2/DDR3 SDRAM UniPHY based Controller does not match with the other Qsys component like Maximum burst size (words) in Avalon-MM Pipeline Bridge? |
| Is there a way to choose which rank to be calibrated first in multiple rank DDR3 SODIMM design? |
| Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(495): the port and data declarations for array port "afi_rrank" & "afi_wrank" do not specify the same range for each dimension |
| Why is the efficiency of the Cyclone V and Arria V hard memory controller lower than expected for single port designs? |
| Why do I see incorrect read data when using a Hard Memory Controller with multiple MPFE ports? |
| Warning (332174): Ignored filter at &lt;variation name&gt;_p0.sdc(679): _UNDEFINED_PIN__driver_core_clk could not be matched with a clock |
| Why does the external memory interface calibration hang after a CvP update when using the DDR3, DDR2 or LPDDR2 UniPHY hard memory controller? |
| Can I share a single PLL for two ALTMEMPHY instances in my design? |
| Which tDQSS timing parameter should be used in the UniPHY LPDDR2 IP Memory Timing tab of the parameter editor? |
| Error (12002): Port "strobe_n_io" does not exist in macrofunction "dq_ddio.ubidir_dq_dqs" |
| Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of (value) |
| How should I place the QDRII/QDRII+ mem_cq and mem_cq_n pins in Arria V GX/GT/ST/SX devices? |
| Are there any issues with the UniPHY LPDDR2 IP address and command pinout ? |
| Can I swap DQ pins of the HMC to ease routing congestion? |
| What causes an MPFE port to lock up? |
| Error (14024): Parameter "mem_if_tcwl" of instance "hmc_inst" has illegal value "TCWL_1" assigned to it. Possible parameter values are: "TCWL_8", "TCWL_7", "TCWL_6", "TCWL_5", "TCWL_4", "TCWL_3", "TCWL_2", "TCWL_0". |
| Critical Warning: *_p0_pin_map.tcl: Failed to find PLL clock for pins *:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE |
| Critical Warning (11887): The following pin &lt;data pin&gt; was placed in a reserved GND location. This may cause decreased performance for HMC. Altera recommends the pin location to be grounded |
| Why is my UniPHY External Memory Interface Toolkit timing out? |
| Critical warning: _p0_pin_map.tcl: Failed to find PLL clock for pins |
| Does the EMIF Toolkit Efficiency Monitor and Protocol Checker support the Arria V and Cyclone Hard Memory Controller ? |
| Are the timing violations on the bonding interface of my Cyclone V or Arria V DDR3 bonded hard memory controller design valid? |
| What is the value of the constantBurstBehavior property in my DDR3 SDRAM Controller with UniPHY? |
| Why is my DDR2 UniPHY controller interface only 50% efficient for back-to-back read or write commands? |
| Warning: Illegal value detected on input clock |
| Why does a delay sometime occur when accessing DDR3 memory ? |
| Why is the UniPHY based memory controller design not meeting timing? |
| Does the ALTDQ_DQS2 IP support LPDDR2 memory? |
| When using the UniPHY-based hard memory controller, why do I see timing violations between the ports on the MPFE block? |
| Warning (10230): Verilog HDL assignment warning at *instance_name*_write_datapath.v(118): truncated value with size to match size of target (1) |
| Why does DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM Altmemphy and UniPHY based controllers violate the maximum refresh interval specified in the memory preset editor in the controller GUI? |
| How do I connect my DDR3 controller to a 72-bit x4 DDR3 RDIMM? |
| Why is the input parallel termination value not shown in the Intel® Quartus® Prime fitter report for Input Pins and Bidirectional Pins? |
| Possible Timing Failure on Designs
Targeting Arria V and Cyclone V Devices |
| How does the Avalon data bus map to the external DDR3 bus for DDR3 with ECC interface? |
| Can I instantiate a master/slave DDR3 UniPHY example design in a top-level wrapper file? |
| ERROR: The supplied JTAG Debug Information (.jdi) file for the project does not appear to match the specified target device as not all nodes have hierarchy info. |
| Is there any issue with DDR, DDR2, DDR3 SDRAM High Performance controller generated testbench regarding dm_delayed signal? |
| Why does avl_ready deassert after avl_write_req is asserted in my DDR3 and DDR2 SDRAM High Performance Controller II IP? |
| Error: The parameter MEM_CS_WIDTH (Number of chip-selects per device/DIMM) must be set to 2 or greater for RDIMM/LRDIMM devices |
| Why does the Avalon bus lock up when simulating a DDR2 SDRAM and DDR3 SDRAM Controller with UniPHY generated in version 11.0? |
| How do I determine the maximum frequency for DDR3 interfaces using an SODIMM? |
| Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY? |
| Fatal Error: Read data comes back but dynamic OCT ctrl is not in read mode |
| Why is CAS latency of 2 or 2.5 not supported for DDR SDRAM Altmemphy or DDR SDRAM High Performance Controller? |
| Why can't I place a DDR3 UniPHY-based controller in quadrant 1 or 2 in a Cyclone V or Arria V SoC device? |
| Why are the Avalon byte enables not implemented in my DDR3 UniPHY controller version 11.0? |
| Critical Warning: BWS group of size 0 |
| Is there any issue with selecting the option Enable Avalon-MM byte-enable signal when generating RLDRAMII Controller with UniPHY? |
| What files do I need to update in my UniPHY controller when OCT sharing is enabled? |
| Why is avl_ready de-asserting after a read or write request? |
| Can I disable option "Enable Avalon-MM byte-enable signals" when implementing DDR3 SDRAM UniPHY based controller IP in Qsys? |
| Possible Simulation Failure in Skip
Calibration Mode |
| EMIF Maximum Frequency Specification
Update for Stratix V |
| Long Term CK Jitter Exceeds Spec
in HPS Memory Interface in Arria V and Cyclone V Devices |
| Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in region
Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver because the destination is in the wrong region |
| Error (15700): Termination calibration block atom "<your_instance>|altera_mem_if_oct_stratixv:oct0|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout |
| Why is ODT asserted for more than one rank in my DDR3 UniPHY controller? |
| Critical Warning: DOFF group of size 0 |
| Is there an issue with Error Correcting Code (ECC) feature in DDR3 SDRAM and DDR2 SDRAM UniPHY based controller in version 11.0? |
| Is there an issue with “Skip memory initialization” option in UniPHY based DDR2 SDRAM and DDR3 SDRAM Controller? |
| Does UniPHY IP support unaligned reads and writes on the AFI interface? |
| Why is the QDRII+ SRAM UniPHY based controller IP not generating QVLD signal for the interface? |
| Does QDRII SRAM UniPHY based interface support or require setup and hold derating for slew-rate like DDR2 SDRAM or DDR3 SDRAM UniPHY based controller IP? |
| Why do I see discontinuity in the read data burst on mem_dq bus even when I do not change the row address during the read operation using DDR3 SDRAM UniPHY and Altmemphy based controller? |
| Error: {instance_name}: Module has too many unassociated clocks ({instance_name}.pll_ref_clk, {instance_name}.afi_half_clk_in). Only one unassociated clock is allowed |
| Calibration Failure Occurs when
RELEASE_CLEARS_BEFORE_TRI_STATES is On |
| Generation Error or Simulation Failure
for VHDL LPDDR2 Interface |
| Possible Internal Error with Arria
V or Cyclone V Designs Using Hard Memory Controller |
| Possible to Select Unsupported Device
Family for LPDDR2 Interface |
| Can the MMR interface be used in conjunction with the Efficiency Monitor in External Memory Interface Intel® FPGA IP? |
| How long does it take for the Intel® PHYLite IP output delay to take effect when performing dynamic reconfiguration? |
| Warning: DQ I/O pins fed by DQS I/O pin assigned different I/O standards |
| Error (11802): Can't fit design in device. |
| Are there any known issues when trying to connect the EMI Toolkit to a design? |
| Why do I see errors when compiling Qsys system for DDR3 UniPHY based controller with Hard Processor System (HPS)? |
| How do I calculate the address range supported by UniPHY DDR2 or DDR3 External Memory Interface IP ? |
| Error (15700): Termination calibration block atom "<your_instance>|altera_mem_if_oct_stratixv:oct0|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout |
| &lt;slave_name&gt;.ctrl_amm_avalon_slave_0 does not have byteenables. Writes from narrow master &lt;master_name&gt;.master may result in data corruption |
| Cyclone V SoC and Arria V SoC Hard Processor System SDRAM calibration fails with the Quartus II software versions 13.1.1 and 13.1.2 |
| Rule C101: Gated clock should be implemented according to the Altera standard scheme |
| Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power |
| Rule C105: Clock signal should be a global signal |
| Postfit Simulation of UniPHY Hard
Memory Interfaces is Not Supported for Arria V Devices |
| Arria V and Cyclone V Hard Memory
Controller Options May Not Function Correctly for Interfaces with
2 Chip Selects |
| Illegal Speed Grade Error with Arria
V and Cyclone V Devices |
| VHDL Post-Fit Simulation Failure
on Stratix V Devices |
| LPDDR2 Timing Closure Problem with
Arria V Devices |
| QDR II and QDR II+ SRAM Controller
with UniPHY IP Core May Not Operate Below 167MHz |
| Warning Messages Displayed for UniPHY
External Memory Interfaces When Compiling for Stratix V Devices |
| What can cause a calibration failure on the odd numbered ranks of a multiple rank DDR3 or DDR4 interface ? |
| How do you use the DQS phase-shift circuit when the memory interface frequency is below the DLL minimum reference clock frequency? |
| Warning : Input frequency violation on DLL instance |
| Error: Output port DATAOUT on atom dqs_in_delay_1 which is a arriav_delay_chain primitive, is not connected to a valid destination |
| How do I determine the failing calibration stage for a Cyclone V or Arria V HPS SDRAM controller? |
| Error: Could not place PHY_CLKBUF {instance_name}:{instance_name}_inst|{instance_name}_0002: {instance_name}_inst|{instance_name}_p0:p0|{instance_name}_p0_controller_phy:controller_phy_inst|{instance_name}_p0_memphy_top:memphy_top_inst|uphy_clkbuf_memphy
Error: PHY_CLKBUF location is occupied |
| Warning (177007): PLL(s) placed in location &ltPLL location&gt do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks |
| How to manually instantiate the hard input FIFO from ALTDQ_DQS2 in Stratix V? |
| How do I view the external memory signals in my HPS SDRAM simulation? |
| Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_mint.cpp, Line: 1869
driver_atom->is_clkbuf() |
| How do I connect csr_debugaccess and csr_burst_count ports generated by DDR3 SDRAM Controller with UniPHY? |
| Is there an issue with "Enable Auto Power Down" option in DDR2 and DDR3 SDRAM UniPHY based controller generated in Quartus II software version 11.0 and 11.0SP1? |
| What is the minimum pulse width timing specification of the global reset signal in UniPHY IP? |
| What is the "minimum pulse width timing specification" of the global reset signal for the UniPHY Controller? |
| Why do I see an efficiency issue when using the Arria V and Cyclone V hard memory controller with DQS tracking enabled? |
| Do I need to make user assignments for Cyclone V hard memory controller ground pins? |
| Why do I get a Fitter error when compiling LPDDR2 soft memory controller? |
| Error (181011): Incompatible on-chip termination settings detected for pins in the DQS group fed by DQS I/O pin "&lt;QK clock pin&gt;". All pins in group must use the same OCT control block. |
| Does Quartus II software support x36 QDRII/II+ SRAM emulation mode in Stratix V devices? |
| Why assertion of reset may cause low probablity lock up of UniPHY NIOS sequencer resulting in incomplete calibration |
| Why is there a "reserved_mem_reserved_pins_for_dk_group" pin in RLDRAM II-UniPHY based controller in the Stratix V device? |
| Does UniPHY External Memory Interface debug toolkit support all the speed grades for Stratix III and Stratix IV FPGA devices? |
| Migrating UniPHY IP from 13.0 SP1
DP5 to 13.1 Resets GUI to Default Values |
| ECC Not Enabled in Cyclone V SoC
HPS Devices |
| Error Messages for UniPHY External
Memory Interfaces in ModelSim Flow for Eclipse |
| Deep Power Down Issue With LPDDR2
Interfaces on Cyclone V Devices Using Hard Processor System |
| An error occurred while linking the project to the device |
| Unable to establish a connection because no memory interface targets exist on the linked device. |
| Why do I see a mismatch between the IBIS simulation model and the actual hardware measurement for the read DQ waveform when using the HPS external memory interface? |
| Why is my DDR3L SDRAM UniPHY based controller design missing some pin assignments? |
| Error (170084): Can't route signal "|altdq_dqs2_stratixv:altdq_dqs2_inst|dqs_enable_int" to atom "|altdq_dqs2_stratixv:altdq_dqs2_inst|dqs_ff" |
| Why does the UniPHY CORDROP_ERROR register show a non-zero value? |
| Error (129029): Input port CLK on atom "&lt;DLL instance&gt;", which is a arriav_dll primitive, is not connected to a valid source File: &lt;project path&gt;/dll.v Line: 53 |
| Does any memory location gets written into in DDR3 SDRAM with ALTMEMPHY in calibration write levleing stage? |
| What is the frequency range of SDRAM output clocks in HPS? |
| Are there any issues with using the UniPHY EMIF toolkit with SOPC builder projects ? |
| Does Cyclone V -C8 device support DDR3 Soft Memory Controller? |
| Critical Warning: <corename>_if0_p0_pin_map.tcl: Failed to find PLL clock for pins if0|p0|controller_phy_inst|memphy_top_inst|afi_half_clk_reg |
| pll_sharing Warning Message May
Appear |
| Simulation of ALTMEMPHY IP with
Cyclone IV Devices Fails |
| Low Probability of Calibration Failure
Following Repeated Resets |
| DDR3 HPS Interfaces Supported Only
to 450 MHz on Arria V SoC ES Devices |
| x8 and x16 HPS Designs not Supported
on Arria V and Cyclone V Devices |
| Write Timing Violation at 550MHz
for QDR II and QDR II+ SRAM Controller with UniPHY |
| Non-leveled DDR2 Topology Fails
Timing with Stratix V Devices for DDR2 and DDR3 SDRAM Controller
with UniPHY |
| Example Design for Arria V with
Hard Memory Interface Uses Wrong Clock |
| Soft Controller May Not Meet Timing
When Data Reordering is Enabled |
| PHY Clock Tree Not Driven by Optimal
PLL Output Counters |
| QDR II/II+ Interfaces Targeting
Arria V Devices Must Use the Nios II-Based Sequencer |
| Are the guidelines to place K and Kn pins for QDRII/+ SRAM interface when implementing the interface with UniPHY based IP different from the ones for ALTMEMPHY based IP? |
| Are there any known issues in ALTMEMPHY-based DDR2 and DDR3 SDRAM memory interface designs that could cause hardware functional failures (memory data corruption)? |
| What is the difference between afi_rdata_en and afi_rdata_en_full signals in UniPHY based DDR2 SDRAM and DDR3 SDRAM Controller? |
| Why do I get timing violation associated with CK clock domain when implement multiple RLDRAM II interfaces sharing a single PLL and DLL? |
| Why is my Arria V QDR II and QDRII+ SRAM controller with UniPHY IP missing a CQn clock signal ? |
| Does the DDR3 High Performance controller II support single-rank, dual-rank, and dual-slot Registered DIMM for Stratix III and Stratix IV devices? |
| Error: Can't place CQn I/O "mem_cq[0]" to a non-CQn I/O location Pin |
| How should I connect mem_ac_parity, mem_err_out_n, and parity_error_n signals in Altmemphy based DDR3 SDRAM High Performance Controller if I do not wish to use the parity feature in DDR3 SDRAM RDIMM? |
| When using UniPHY IP in Stratix V devices, what are the options for changing the calibrated OCT termination values from the default values ? |
| Does the Advanced clock phase control adjustment in the HPS DDR3 work? |
| Error (170084): Can't route signal "~GND" to atom "< dqs_oct_alignment~_Duplicate>" |
| Why is the "Additional CK/CK# phase" option grayed out inside the MegaWizard GUI for the Stratix V device? |
| Is there any issue with Cyclone V SoC HPS support for DDR2 design which has width less than 24 bits? |
| Does Stratix V QDRII/+ SDRAM Controller at full rate have timing closure issue? |
| Why is Report DDR timing report missing when I have multiple instances of a wide external memory interface? |
| Why does the time interval for four active windows during RTL simulation not match the tFAW setting in the Arria 10 FPGA DDR4 IP GUI? |
| Can the HPS DDR3 controller local-to-memory address mapping be changed in the simulation fileset? |
| Why do I see long refresh cycles when using DDR3 SDRAM Controller with UniPHY in Stratix V devices? |
| Why do I see timing violations and ignored clock constraint warning messages in my UniPHY-based DDR3, DDR2, QDRII/+, or RLDRAM II memory controller design? |
| Why is the SOPC Builder system generation only successful for the first attempt but fails for the successive attempts in Quartus II software version 10.0 as well as 10.0 SP1? When it fails, the SOPC Builder hangs during the system generation at "Info: <module_name_UniPHY>: No Extra Settings:" |
| How do I take the package delay into account in the board skew parameters of a Stratix V DDR3 UniPHY controller GUI? |
| Why can’t I merge PLLs for two different instances of the ALTMEMPHY IP? |
| Why do the External Memory Interface DQ and DQS waveforms sometimes have poor signal quality when measured at the FPGA pin on a memory read ? |
| Why is my Arria 10 DDR4 design failing compilation in the fitter when I choose "Automatically select a location" for ALERT# pin placement? |
| Is UniPHY based DDR2 SDRAM memory controller supported for Cyclone IV and Arria II GX FPGA devices? |
| Why do I get minimum period timing violation in UniPHY based DDR3 SDRAM Controller on Stratix V device? |
| How do I configure my Micron Hybrid Memory Cube (HMC) Bus Functional Model (BFM) to operate in half-width mode (8 lanes)? |
| Are there any known issues with tCCD_S behavior in the Arria 10 FPGA DDR4 IP? |
| Are single bit errors corrected when the <strong>Enable Error Detection and Correction Logic</strong> option is selected and the <strong>Enable Auto Error Correction</strong> option is disabled in the DDR3 SDRAM controller with UniPHY? |
| What is the maximum burst length for the hard memory controller? |
| How can I implement the DDR2 SDRAM or DDR3 SDRAM UniPHY PHY with my custom memory controller (instead of using the integrated Altera high-performance memory controller)? |
| What tools should I use to enable my memory to interfaces with my Altera FPGA? |
| Why is the hard memory controller failing calibration in a Arria V ES device? |
| Why do I get fitter errors when compiling a Qsys DDR3 UniPHY based controller design? |
| Error:129001 Input port OFFSET on atom "|dll_ctrl_a_wys", which is a statixv_dll_offset_ctrl primitive, is not legally connected and/or configured |
| Why is the memory device I am using not included in the memory preset list? |
| Simulation stalls when global_reset_n is toggled early in Arria 10 DDR4 PHY-Only IP simulation |
| Error (129001): Input port DQSDISABLEN on atom "|hierarchy|dqs_delay_chain", which is a stratixv_dqs_delay_chain primitive, is not legally connected and/or configured |
| Why can I assign more than a 32-bit data width to the Arria V Hard Memory Controller ? |
| When does the UniPHY DDR3 IP use an I/O standard of SSTL-15 Class II ? |
| Why do I see timing problems reported when using derive_pll_clocks using UniPHY-based memory controllers? |
| Where can I find RLDRAM 3 External Memory Interface IP for Altera FPGAs? |
| Why do I get no result for "Report DDR" in TimeQuest for DDR3 SDRAM UniPHY based controller? |
| Is there any known issue using the On-chip parallel termination (RT) with UniPHY IP ? |
| Selected input mode termination value for data bus is not valid. Please select a value of 50 ohm or higher. |
| What is the largest capacity DDR3 device supported by the Arria V and Cyclone V FPGA UniPHY memory IP ? |
| Why does the Arria 10 External Memory Interfaces IP FPGA IO Settings for Data Bus Input Mode not support lower values than 60 ohms in the Quartus Prime software version 16.1.1 for DDR4 and QDRIV protocols? |
| How is it determined if I/O banks are adjacent for External Memory Interface pin-outs in Intel® Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 FPGAs? |
| Are there any known issues with tCCD_S behavior in the Arria 10 FPGA DDR4 IP? |
| Why does the Arria 10 EMIF IP remain in reset during the second RTL simulation run when using the Abstract PHY ? |
| What is the DLL jitter specification for external memory interfaces and does the DLL jitter change depending on the frequency of operation? |
| Why do I get an error when selecting a rank of 4 with 4 chip selects for a DDR3 LRDIMM? |
| What is the maximum operating frequency for an external memory interface using the custom PHY? |
| Why can't two center PLLs drive two different memory controllers with UniPHY at the bottom of a Stratix V device? |
| Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY based controller |
| Why are some pins of adjacent banks placed on different edges of the package? |
| Warning (15610): No output dependent on input pin "avl_burstbegin" |
| Why am I unable to simulate the design given with External Memory Interface handbook chapter "Using High-Performance Controller II with Native Interface Design" under Altmemphy design tutorial? |
| Can I assign DM pin to any DQ pin location in a DQS group? |
| Error: Output port OUTCLK of stratixv_phy_clkbuf atom "Hierarchy|{instance_name}_p0_memphy_top:memphy_top_inst|uphy_clkbuf_memphy" has one or more illegal fan-outs. |
| Additive Latency Not Supported for
HPS Hard Memory Controller in Arria V and Cyclone V SoC Devices |
| Why do I get two chip selects when I generate a UniPHY DDR3 registered DIMM single rank configuration? |
| Warning-[SIOB] Select index out of bounds. Following select index is out of declared bounds : [x:0]. In module instance: &lt;inst_name&gt;. In module :&lt;module_name&gt; &ltpath&gt/alt_ddrx_bank_tracking.v", 612: int_cmd_do_activate_cached[x] |
| Is there any known issue that can cause calibration failure on designs with full-rate QDRII/II+ SRAM and RLDRAM II UniPHY based controller created in the Quartus II software version 10.0SP1 and earlier? |
| Does UniPHY controller write back the data to memory when double bit error happens with enable ECC option turned ON? |
| How do I connect the clock and reset for an Arria 10 HPS hard memory controller when the FPGA is not programmed? |
| Critical Warning (181053): PLL output counters driving PHY_CLKBUF {Hierarchy_Path}:pll0|uphy_clkbuf_memphy are not recommended for use in the memory IP PHY clock tree and timing models may not be correct. |
| Why do I see mem_k and mem_k_n clock pair as unconstrained output ports in TimeQuest when I implement QDRII SRAM UniPHY based controller? |
| How does TimeQuest take DQS delay chain settings changes into account when reporting timing for ALTDQ_DQS Megafunction? |
| Does ALTMEMPHY based DDR3 SDRAM controller IP support automatic slew rate deration for a DDR3 SDRAM device with speed grade greater than or equal to 667MHz at AC175 specification? |
| Arria 10 EMIF Simulations May Failwith Certain Versions of Riviera-PRO |
| The Quartus II software verion 14.1 does not include DDR3 I/O placement rules for MAX 10 devices |
| Errors in Post-Fit Simulation of
EMIF Interfaces on Arria V and Cyclone V Devices |
| Enabling slow slew rate option for EMIF Addr/Cmd and CK |
| Are there any placement restrictions for the Intel Stratix 10 HPS EMIF IP PLL reference clock and RZQ pin? |
| Warning: When the address/command signals and the memory clock signals do not use the same slew rate setting, signals using the "Slow" setting are delayed relative to signals using "Fast" setting |
| Why is the tRTP timing parameter box missing from the Intel® Stratix® 10 and Intel Arria® 10 EMIF IP GUIs? |
| Why is the traffic generator 2.0 option for External Memory Interfaces IP disabled in the Intel® Quartus® Prime Pro Edition version 18.0? |
| How is the address map ordering of the Avalon bus to the DDR4 memory defined for the Intel® Stratix® 10 External Memory Interfaces IP ? |
| Critical Warning (176647): DLL atom "{instance_name}|altera_mem_if_dll_stratixiv:dll0|dll_wys_m" dll_wys_m" is using a clock period of "value 1" ns, which is outside the valid range for its configuration mode. When the delay buffer mode is "HIGH" and the delay chain length is "8", the valid range is from "value 2" ns to "value 3" ns. |
| How do I resolve timing violations on the quarter rate to half rate clock transfer in my UniPHY-based DDR3 controller design? |
| Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command |
| Error: couldn't read file "<variation_name>_phy_ddr_timing.tcl": no such file or directory while executing "source "<variation_name>_phy_ddr_timing.tcl" (file "<sub-directory>/<variation_name>_phy_ddr_timing.sdc" line 33) |
| Why do I not see DQS tracking signals when I implement UniPHY based DDR3 SDRAM Controller above 533MHz? |
| Which locations are being used during calibration in ALTMEMPHY with leveling? |
| Why does quarter rate DDR3 UniPHY based controller design show low read efficiency? |
| ODT signal does not toggle when ODT Rtt nominal is off and Dynamic ODT (Rtt_wr) is on |
| Why is a global signal assignment to <instance_name>|s0|rst_controller|alt_rst_sync_uq1|reset_out being ignored by my UniPHY-based DDR3 controller IP? |
| Why does my DDR3 Uniphy *|pll_c2p_write_clk clock disappear from my TimeQuest reports during certain compilations? |
| How do I setup my Hybrid Memory Cube Controller (HMCC) simulation to handle larger than 2GB memory size? |
| Why do I have to disable the DM pins generation in the DDR3 SDRAM High Performance Controller or Altmemphy IP Megawizard when implementing DDR3 SDRAM controller in x4 mode in Stratix III or Stratix IV devices? |
| Why do I see failures when implementing multiple external memory interfaces in Arria 10 devices? |
| Why do I see the error message in the MegaWizard when I try to generate UniPHY based DDR3 SDRAM controller for Stratix V device? |
| Why has the UniPHY CSR interface access latency increased in 11.0 and later version of the IP compared to 10.1 version of the IP? |
| Possible Calibration Error for DDR2
and DDR3 Interfaces on Arria V, Cyclone V, and Stratix V Devices |
| What reference plane should the DDR4 Vref bypass capacitors connect to on my PCB? |
| Error: {variation_name}_p0_pin_map.tcl: Failed to find PLL reference clock |
| Why are bidirectional mem_dbi_n ports created when the 'Enable DM Pins' option is selected in the Arria 10 DDR4 controller? |
| Why are the Arria 10 DDR4 Mode Register 4 (MR4) write/read preamble bits set incorrectly? |
| Can I have more than one DDR3 SDRAM (with leveling) memory interface located in a single IO sub-bank for Stratix IV device family? |
| EMIF Maximum Frequency Specification
Update |
| EMIF Generation for Arria V or Cyclone
V Devices Requires Stratix V Device Database to be Installed |
| New Restrictions on I/O PLL Configuration Imposed in 15.1 for Arria 10 EMIF IP |
| Warning Message Displayed When Driving
User Logic with Custom PLL in Hard Memory Interface |
| Does the Arria 10 external memory interface IP support DDR4 Write CRC ? |
| Why are some DDR4 signals unconstrained in TimeQuest? |
| Why do the DDR4 memory interface signals show values of ‘hxx in the waveforms of the example testbench simulation? |
| How can the Intel® Stratix®10 MX HBM2 controller efficiency be improved? |
| What is the flow to modify the Intel® Stratix® 10 SoC Development Kit HPS DDR4 width and ECC configuration using the Golden Hardware Reference Design project as the starting point? |
| Are there any placement restrictions for the Intel® Arria® 10 HPS EMIF IP PLL reference clock and RZQ pin? |
| What is the pull-up resistor guideline for the DDR4 alert_n signal? |
| Internal Error: Programmable pre-emphasis option is set to 1 for pin dut_mem_mem_par(0)~pad, but setting is not supported by I/O standard SSTL-12 with Slew Rate 0 |
| Is there an issue with device migration in Cyclone IV devices when implementing DDR SDRAM or DDR2 SDRAM interface with ALTMEMPHY based controller? |
| Error (169026): Pin oct_rzqin is incompatible with I/O bank {bank}. It uses I/O standard SSTL-135, which has VCCIO requirement of 1.35V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 2.5V. |
| Error: The specified Memory clock frequency exceeds the Memory device speed grade of 533.333 MHz. Please increase the Memory device speed grade (in Memory Parameters tab) or decrease the Memory clock frequency. |
| Why are some DDR4 signals unconstrained in TimeQuest? |
| Why do I see an extra read data valid assertion on the Arria 10 EMIF MMR interface? |
| Are there any Arria 10 DDR4 IP parameters that changed in the Quartus Prime software version 15.1? |
| Why I can not find AN435:Using DDR and DDR2 SDRAM Devices in Stratix III and Stratix IV Devices on Altera website? |
| Why do I see the error message from External Memory interface tool kit when I connect through JTAG? |
| Why am I seeing a difference in the option of number of chip selects for DDR3 UniPHY IP generated in Quartus II V12.0 and V13.0 and later versions? |
| Can unused HPS EMIF pins be used as FPGA GPIOs? |
| Why is the Cyclone V SoC Device SDRAM interface Vref pin voltage incorrect ? |
| How do I resolve Arria 10 External Memory Interfaces DDR4 IP read capture timing violations ? |
| Is the Burst Chop 4 (BC4) support in Arria 10 External Memory Interface IP? |
| Warning: Ignored assignment: set_false_path -from [get_pins -compatibility_mode {*_alt_mem_phy_inst|*mmc|mimic_done_out*}] -to [get_keepers {*_alt_mem_phy_inst|*seq_wrapper|*seq_inst|*dgrb|*v_mmc_seq_done_1r}] |
| Error (10149): Verilog HDL Declaration error at core_debug.sv(1): identifier "seq_core_debug_pkg" is already declared in the present scope |
| Why do I get 3 unconstrained clocks in TimeQuest for my DDR3 controller in Arria V devices? |
| Default tCCD for LPDDR2 Devices
Hard Codes to 2 Cycles |
| Memory Controller May Become Unresponsive
for LPDDR2 Interfaces Using Deep Power-Down Mode |
| What is the default Local-to-Memory address mapping in the HPS SDRAM controller? |
| Is there an issue with sharing OCT between master and slave UniPHY based controller IPs for Stratix V RLDRAMII and QDRII? |
| Is DDR2 SDRAM with HPS Hard Controller supported in Arria V SoC Devices? |
| VHDL Postfit Simulation Not Supported
for Arria V and Cyclone V Designs with Hard Memory Controller |
| Error: Slow slew rate is not compatible with on-chip output termination for the address/command bus. Either turn off output termination (if possible), or use Fast slew rate. |
| DQS# Enable Option Must be Enabled
for LPDDR2 Interfaces |
| Low Frequency Limit for DDR2 and
LPDDR2 on Arria V and Cyclone V Devices |
| Cannot Generate DDR3 RDIMM IP for
Stratix IV or Stratix V with RC8–RC15 Set to Non-Zero Values |
| Should I use an industrial marked FPGA with my industrial temperature rated DDR SDRAM? |
| Why does Quartus II Fitter automatically fit a mem_dq on preassigned DM pin on Cyclone IV device? |
| Can I enable Multiple controllers clock sharing in ALTMEMPHY based High Performance Memory Controller in SoPC builder for Cyclone III and IV device? |
| Critical Warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os |
| Warning-[PCWM-W] Port connection width mismatch &ltpath_name&gt;/SdramController_PLL_Master_phy_alt_mem_phy.v, 1395"clk". The following 1-bit expression is connected to 2-bit port "scan_din" of module "SdramController_PLL_Master_phy_alt_mem_phy_clk_reset", instance "clk" Expression: scan_din[0] use +lint=PCWM for more details |
| Error: **_emif_a10_hps_0: PLL reference clock frequency of 25.0 MHz is invalid. Please select another value, or enable the option to use the recommended value. |
| Why have the Arria 10 External Memory Interfaces IP Slew Rate parameters been removed in the Quartus Prime software version 15.1 ? |
| Arria V and Cyclone V Devices May Display Small DQS Enable Windows |
| Is there a problem when simulation ALTDQ_DQS2 megafunctions generate by the Quartus II version 12.0? |
| Controller Bonding is Not Available
in the Hard Memory Interface |
| Error Message for Auto Power Down
Cycles Does Not Indicate Valid Range |
| Timing Closure for Soft LPDDR2 Interfaces
May Not be Robust |
| Simulation of Arria 10 Designs With Questa Advanced Simulator Version 10.4b
May Hang Under Certain Circumstances |
| Some Arria 10 EMIF Designs May Fail Simulation with NCSim and Riviera-PRO |
| Simulation Fails with PLL Clocks
Out of Synchronization for UniPHY External Memory Interfaces |
| Critical Warning (19028): HPS DDR oct_rzqin pin is placed in a location not supported by HPS Early IO release. If you plan to use Early IO release, place the oct_rzqin in the IO bank 2K. |
| Why is the Reserved Value in the Altera PHYLite Dynamic Reconfiguration Address Map different during simulation than the one published in the user guide? |
| Why are there missing Hex files when I simulate DDR3 SDRAM Controller with UniPHY? |
| Error (175020): Illegal constraint of pin to the region : no valid locations in region |
| Why is Synchronizer Identification assignment for UniPHY based QDRII controller ignored by fitter? |
| Error (10231): Verilog HDL error at <variation_name>_memphy_top.v(305): value cannot be assigned to input "pll_mem_clk" |
| Error: Node instance "encoder_inst" instantiates undefined entity "alt_mem_ddrx_ecc_encoder_32" |
| Can I use Report DDR for ALTDQ_DQS2 megafunction? |
| Why are the timing margins the same values for all corners when performing Report DDR in TimeQuest for Arria 10 external memory interfaces? |
| Why is there a mismatch between the local Avalon interface data width and memory interface data width when generating UniPHY based DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM and RLDRAMII controller IPs? |
| How can the auto-precharge feature of the Intel® Stratix® 10 DDR4 hard memory controller be used to achieve the highest memory bandwidth? |
| DDR2 and DDR3 Designs Using Hard
Memory Controller May Not Close Timing on Arria V and Cyclone V
Devices |
| Simulation of Arria 10 Designs With Abstract PHY May Hang Under Certain
Circumstances |
| Possible Syntax Error When Running Abstract PHY Simulation with ModelSim and
Tcl |
| Why do I get Burst Chop when accesing DDR3 SDRAM using Altmemphy based DDR3 SDRAM Controller? |
| Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6.cpp, Line: 832 |
| Possible Timing Closure Difficulty for QDR II Interfaces on Arria 10
Devices |
| Warning: Ignored filter at instance_name_p0.sdc(675): {instance_name_clkout[0]} {instance_name_clkout[1]} could not be matched with a clock |
| Change to tWPRE Timing Might Cause
Failure for DDR2 and DDR3 Interfaces on Arria V and Cyclone V Devices |
| Possible Read/Write Errors for DDR2
and DDR3 Hard Memory Controllers on Arria V and Cyclone V Devices
at Low Vcc and Extreme Temperatures |
| Error May Occur When Generating
Hard Memory Controller in Qsys |
| Timing-Related Warning Messages
for DDR2 and DDR3 SDRAM Controller with UniPHY When Sharing PLLs
on Stratix V Devices |
| Example Project Fails to Simulate
When HardCopy Compatibility is Enabled for UniPHY External Memory
Interfaces |
| Stratix V QDR II and QDR II+ SRAM
Controller with UniPHY and RLDRAM II Controller with UniPHY Memory
Interfaces May Exhibit Write Timing Failure |
| Clock mem_cq_n Not Used for QDR
Interfaces on Arria V and Cyclone V |
| DDR3 Interfaces with Multiple mem_ck
signals May Produce No-Fit Errors |
| Some DDR2 and DDR3 EMIF Designs Targeting Arria 10 Devices May Fail Simulation
with NCSim and Riviera-PRO. |
| RTL Modification Required for Top/Bottom
Bonding on Arria V and
Cyclone V Devices |
| ODT Signal Not Functioning Correctly
for DDR2 and DDR3 Hard Memory Interfaces Targeting Arria V or Cyclone V
Devices |
| Possible Timing Violations with
Ping Pong PHY on Arria 10 Devices |
| External Memory Interface Handbook: Known Issues |
| Timing-Related Warning Messages
for QDR II and QDR II+ SRAM Controller with UniPHY and RLDRAM II
Controller with UniPHY When Sharing PLLs on Stratix V Devices |
| Why is the memory reset output port unconstrained in the memory controller? |
| Why do I see a Qsys warning for the pll_sharing conduit even when the PLL sharing mode option is set to 'No Sharing' in the UniPHY Megacore settings? |
| Does the UniPHY-based DDR3 controller support dual-slot, quad-rank DDR3 RDIMM or UDIMM? |
| Is there any issue with DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM High Performance Controller or High Performance Controller II in Arria II GX devices which may cause hardware failure? |
| Higher Delays and Skews Expected
for UniPHY External Memory Interfaces Corner I/Os in Stratix V Devices |
| Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally |
| How should the CKE signal be terminated for DDR3 and DDR4 interfaces? |
| What are the VREF requirements for a DDR4 interface using the Arria 10 or Stratix 10 External Memory Interfaces IP ? |
| Why doesn't the mmr_slave_readdatavalid signal de-assert when accessing the MMR ECC register? |
| Why doesn't the Intel® Arria® 10 and the Intel Stratix® 10 QDR-IV IP issue burst accesses? |
| Why doesn't the Intel® Arria® 10 or the Intel Stratix® 10 DQ/DQS x4 configuration follow the pin-out placement documentation and the DQ/DQS Pins view in the Intel Quartus® Prime Pin Planner? |
| Why doesn't the Intel® Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 EMIF IP calibration sequencer start calibration on the second EMIF IP if the first EMIF IP in the same I/O column fails calibration? |
| Why doesn't the Intel® Arria® 10 HPS EMIF and Stratix® 10 HPS EMIF IP generate a simulation example design directory? |
| What is the behavior of the traffic generator status signals in the Intel® Arria® 10 and the Intel Stratix® 10 EMIF IP example design? |
| Timing Closure for Hard LPDDR2 Interfaces
May Not be Robust in Cyclone V SoC Devices |
| Can I create my own customer preset when using DDR2 and DDR3 SDRAM controller with UniPHY? |
| How to share OCT between QDRII and QDRII+ SRAM Controller with UniPHY and DDR3 SDRAM Controller with ALTMEMPHY? |
| Calibration May Fail on Some DQS
Groups for External Memory Interfaces Targeting Some Arria V Devices |
| Possible Timing Failure on Certain
Paths in Designs Targeting Cyclone V Devices |
| Possible No Fit Errors on Cyclone
V HPS Devices |
| Simulation Fails for UniPHY External
Memory Interfaces with “Undefined System Task Call” Error |
| Simulation Fails for UniPHY External
Memory Interfaces when Generating VHDL for Designs Using Nios II-based
Sequencer |
| Driver Margining Not Compatible with Periodic OCT Recalibration in Arria 10
EMIF IP |
| Possible VHDL Simulation Failure
with ModelSim-SE on Arria 10 Devices |
| DQS Tracking Disabled Below 667
MHz For Some Arria 10 Devices |
| Why do I see the message "Connection between avalon_master.writedata and avl.avl_wdata must be width of [8,16,32,64,128,256,512,1024] with the DDR2(3) SDRAM Controller with UniPHY? |
| What is different between Dynamic ODT and Dynamic OCT when interfacing DDR3 SDRAM with Stratix III or Stratix IV FPGAs? |
| Why can't some DDR3 HMC control registers be read or written by the CSR interface? |
| Error (332000): can't read "local_pll_driver_core_clk": no such variable |
| Why my DDR3 HMC example designs targeting Arria V devices with C5 speed grade at 533MHz failed timing? |
| How should I connect OCT calibratoin pins (Rup and Rdn) in Altera DDR/DDR2/DDR3 High Perfomance Memory Controller design? |
| Why do I see data errors on my HPS LPDDR2 interface? |
| Arria V and Cyclone V Soft Controllers
May Not Meet Frequency Targets if CSR or ECC Enabled |
| Stratix V Device Handbook: Known Issues |
| For some MAX 10 device designs, the Fitter causes an abnormal exit during the Fitter stage when listen_to_nsleep_signal is set |
| Error: Bidirectional I/O uses parallel termination, but does not have dynamic termination control connected |
| Unable to establish a connection because no memory interface targets exist on the linked device |
| Are there any concern on DDR timing using Altera EMIF (External Memory Interface) IP if my design fails DCD (Duty Cycle Distortion) compliance testing? |
| Are there any issues with the DDR/DDR2 specification for Cyclone II C7 and C8 speed grades that were published in AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices version 1.0? |
| Is there any knonw issue for simulation StratixIII Altmemphy DDR2? |
| Why did my DDR3 UniPHY example design fail simulation? |
| Are there any know issues with AltMemPHY IP with mutliple rank external memory systems? |
| Error (175005): Could not find a location with: RST_SRC_ID of &lt;value&gt; |
| Error: missing operand at _@_ in expressin "_@_/1000.0" |
| ECC Enabled Automatically in Cyclone V
SoC HPS Devices |
| LPDDR2 Interfaces on Arria V SoC
Devices May Fail Postamble Timing |
| Certain I/O Pins Should be Grounded
for Cyclone V Hard Memory Controller Operation |
| EMIF Debug Toolkit Not Functional
for Interfaces Targeting HPS Hard Memory Controller in Cyclone V
SoC Devices |
| Hardware Failure with LPDDR2 Hard
Memory Controller on Cyclone V Devices at 300MHz and 333MHz |
| Some DDR4 LRDIMM Hardware Configurations May Fail Calibration |
| Simulation Example Design Fails
and Produces Warnings |
| Deep Power Down Issue With LPDDR2
Interfaces on Cyclone V Devices |
| TimeQuest May Incorrectly Report
Timing Failure for Hard Memory Interface on HPS Subsystem for Cyclone V SoC
Devices |
| Is there an issue after hard memory controller design without specific INI file being programmed on Arria V ES device ? |
| Does the Max 10 UniPHY IP support SDR SDRAM or SRAM? |
| Why do I see the outdated files in the IP core summary of the compilation report? |
| Why I am seeing the following warnings when I try to run RTL simulation using 3rd party DDR3 vendor model in Modelsim? |
| Are there any factors that can affect the efficiency performance of the UniPHY LPDDR2 IP? |
| What information does the Efficiency Monitor display in the EMIF Toolkit? |
| For EMIF Interfaces on Arria 10 Devices, the Duplicate Qsys Button results in an Error Message |
| Incorrect Pin Mapping for DDR3 LRDIMM
and LPDDR3 in Arria 10 EMIF |
| Error May Occur When Simulating VHDL Designs With MMR Enabled Using VCS-MX |
| EMIF Toolkit Error May Occur for Multiple Interfaces in the Same Column with
the Same Interface ID |
| Is there any issue when instance the DDR3 hard IP core? |
| Altera PHYLite for Parallel Interfaces IP Core User Guide: Known Issues |
| Why DDR3 ODT fails in simulation with denali? |
| DDR2 Interfaces on Cyclone V SoC
Devices May Fail Read Capture Timing |
| PLL Master Required for Simulation
of PLL Slave for UniPHY External Memory Interfaces |
| ECC and CSR Designs May Fail in
Simulation or Hardware |
| Simulation Fails When Enable Auto
Error Correction Option Enabled |
| Enable Avalon-MM Byte-Enable Signal
Option Not Functional for RLDRAM II Controller with UniPHY |
| RLDRAM II Controller with UniPHY
Simulation fails in Riviera-PRO |
| Cyclone V Hard Memory Interface
Does Not Provide Fitter Support |
| Self-refresh Not Working Properly
for Single-rank DDR3 DIMMs |
| Full-rate QDR II and RLDRAM II Are
Not Supported for Arria V |
| No Error Message is Displayed for
Invalid Configuration |
| Error Can Occur When Using Multiple EMIFs in a Single Column and Sharing RZQ
Pins |
| VHDL Simulation of Arria 10 EMIF IP with Riviera-PRO May Fail to Progress
Under Some Circumstances |
| Arria 10 EMIF IP for QDR-IV Using Address Inversion May Fail in
Hardware |
| False Timing Failures in QDR-IV
Interfaces on Arria 10 Devices |
| VHDL-Only Simulation Not Supported
for QDR II and QDR II+ SRAM Controller with UniPHY and RLDRAM II
Controller with UniPHY |
| NativeLink Simulation in UniPHY
External Memory Interfaces fail for VHDL Output |
| In DDR2 and DDR3 SDRAM Controller
with UniPHY, Example Designs Without DM Pins Enabled Will Fail |
| Simulation of Example Designs Can
Fail or Produce Warnings for UniPHY External Memory Interfaces |
| Example Design Simulation for UniPHY
External Memory Interfaces May Fail in NC Sim |
| Fitter Error When Compiling DDR2
Designs Below 240MHz in DDR2 and DDR3 SDRAM Controller with UniPHY |
| Can F1152 and F1517 packages in Stratix IV GX devices support x32/x36 DQS/DQ group? |
| Why does my hard memory controller example design simulation fail? |
| Why DDRx High Performance Controller doesn't work on the hardware when certain Global Synthesis Option Switches of Quartus II software has been changed from its default setting? |
| Do I have to connect VREF pin of the I/O bank where mem_clk pins are located when implementing ALTMEMPHY based IP in Arria II GX devices? |
| Why do the DQS and DQSn signals generated by the DDR SDRAM and DDR2 SDRAM High-Performance Controllers I for write operations have an additional pulse at the end of a write burst? |
| How can I change the test loop count of the Arria10 EMIF IP example driver? |
| Why does my ALTDQ_DQS2 design have conflicting warning messages? |
| How can I make parallel On Chip Termination assignment to the CQ and CQn bi-directional pins of the Legacy QDRII SRAM Controller in Stratix II devices? |
| Why is the efficiency of DDRx UniPHY controller version 11.0 worse than the efficiency of the 10.1 version of the controller? |
| Critical Warning: <slave_DDRx_instance_name>_pin_map.tcl: Failed to find PLL clock for pins mem_if|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_valid_predict[0].qvld_rd_address[0] |
| You May Encounter Difficulty Achieving Timing Closure for QDR-IV Interfaces on Arria 10 Devices |
| DDR3 VHDL Simulation in Max 10 Fails
with Aldec Riviera-PRO |
| Limitations on Support for pre-11.1
UniPHY External Memory Interfaces |
| Arria V and Cyclone V HPS Designs
May Fail to Compile with NC-Sim |
| Why does the Report DDR section in TimeQuest only report 10 paths? |
| Why are the mem_dm pins unconstrained in my Stratix III DDR2 UniPHY design in 11.1? |
| Why is Quartus II software version 10.1 not able to fit ALTMEMPHY based DDR2 SDRAM High Performance Controller generated by Quartus II software version 10.0? |
| Memory IP on Stratix V Devices Does
Not Support Frequencies Below 150 MHz |
| Arria V Soft DDR2 Interfaces Support
Simulation and Compilation Only |
| Center PLL in Arria V Cannot Drive
Two Independent PHY Clock Networks |
| Why am I receiving a warning message when I compile for the advertised DDR2 speeds in the -7 and -8 speed grade Cyclone II FPGAs in Quartus II versions 5.0SP1 and lower? |
| Why are mem_ck and mem_ck_n pins missing in the pin planner for Hard Memory Controller in some Cyclone V devices? |
| Why does the DDR3 Micron MT41J64M16LA memory preset specify the incorrect data width? |
| Error (165011): altmemphy pin placement was unsuccessful |
| Why devices faster than 533MHz require manual derating? |
| Why does the c5gt_pro_goldentop.v file in the Cyclone V GT installation kit include ground connections for the hard memory controller? |
| Bonding Does Not Work for Multiple
MPFE Ports in Hard Memory Controller |
| Failure May Occur For LRDIMM Designs
Simulated with NCSIM and Targeting Stratix V Devices |
| For Versions Earlier than 14.0,
Problems May Occur With DDR3 LRDIMM Interfaces on Stratix V Devices |
| Dynamic ODT Tables Are Incorrect
for Single-Slot Quad-Rank DDR3 Interfaces Targeting Stratix V |
| Compilation Fails When Bonding Feature
is Enabled |
| Calibration May Fail Without Issuing
CAL_FAIL Signal |
| Minimum Pulse Width Timing Failures
for UniPHY External Memory Interfaces |
| Multi-cast Write Control Not Supported |
| Simulation with NC Sim or Riviera-PRO
Fails with an Elaboration Error for UniPHY External Memory Interfaces |
| Some DQ Group Locations Are Not
Usable in Cyclone V |
| Quartus Compilation Error |
| Calibration Fails for QDR II/II+
Designs Targeting Stratix V Devices |
| DDR3 Quarter-Rate Is Not Supported
for Cyclone V Devices |
| Limitations in Support for 400MHz
DDR3 Hard Memory Controller With MPFE Interfaces Targeting Cyclone
V Devices |
| Arria 10 EMIF IP Does Not Support Qsys Testbench Generation
Flow |
| Diagnostics Tab Displays Incorrect Controls |
| Generate Example Design Button May Invoke a Qsys Error Message Under Certain
Circumstances |
| Arria 10 EMIF IP is Not Fully Verified with VID Devices in 15.1 |
| The Traffic Generator May Fail When Multiple EMIF Interfaces Occupy the Same Column on an Arria 10 Device |
| Possible Timing Failures for LPDDR2
Designs on Cyclone V -7 Speed Grade Devices |
| Quarter-rate DDR3 Designs Targeting
Arria V Devices at 667 MHz May Fail Timing |
| For DDR2 and DDR3 SDRAM Controller
with UniPHY, Quartus II Software Cannot Read .mif File for PLL |
| Reduced Clock Rate Specification
for Column and Row I/Os |
| Cannot Share One PLL/DLL/OCT Master
with Multiple Slaves in Qsys for UniPHY External Memory Interfaces |
| Why there is a warning or error message " (vlog-2256) Event expressions should result in a singular type" when I compile <instant>_phy_alt_mem_phy.v in EDA simulation tools? |
| How does UniPHY-based DDR3 controller assert the refresh command for multiple chip selects interface? |
| Why is the PCI Express to DDR2 for Arria II GX Reference Design given by Altera not compiling successfully? |
| For DDR2 and DDR3 SDRAM Controller
with UniPHY, Designs Without Leveling Fail in Stratix V Devices |
| DDR2 and DDR3 SDRAM Controller with
UniPHY Example Design Fails as a Slave |
| DDR2 and DDR3 SDRAM Controller with
UniPHY Simulation Fails in Riviera |
| NativeLink Simulation for UniPHY
External Memory Interfaces fails for VHDL Output |
| Must Enable Support for Nios II
ModelSim Flow in GUI for DDR2 and DDR3 SDRAM Controller with UniPHY
and RLDRAM II Controller with UniPHY |
| What is the difference between ‘Number of ranks per slot’ and ‘Number of chip-selects per device/DIMM’ for DDR3 RDIMM and LRDIMM? |
| How do I select a data width of 16bits for the DDR3 SDRAM UniPHY IP in the Cyclone V EPE IP tab? |
| Memory Parameter Presets May Not
Appear in Parameter Editor |
| EMIF Toolkit Fails With Error Message |
| Hard Memory Interface May Fail VHDL
Simulation in Arria V and Cyclone V Devices |
| DDR2 and DDR3 SDRAM Controller with
UniPHY User Guide Contains Imprecise Clock Information |
| ECC Logic Always Enabled in Controller
when CSR is Enabled |
| Possible Internal Error During Compilation
for MAX 10 Devices |
| Deep Powerdown Mode Causes Failure
of LPDDR2 Interface on MAX 10 Devices |
| DDR2 and DDR3 SDRAM Controller with
UniPHY User Guide Contains Incorrect Clock Information |
| Can "avl_size" interface have value of non power-of-2 ? |
| Why does the High Bandwidth Memory (HBM2) Interface IP example design in the Intel® Stratix® 10 MX FPGA show min pulse width violation? |
| Why does the avl_ready signal stay low when using the hard memory controller with multi-port front end port widths of 128 bits? |
| What are the initial criteria for implementation of DDR3 SDRAM Controller with UniPHY design at 533MHz in HardCopy IV GX? |
| Why do I see fitter or Timequest warnings about missing or ignored clocks when using UniPHY based external memory Interface IP in a Qsys project? |
| Are there any known issues with the Registered DIMM (RDIMM) variant of DDR3 High Performance Controller IP in Quartus II software versions 9.1SP1 and SP2? |
| Why does my DDR3 controller simulation fail with the Aldec simulator? |
| Why does the VHDL wrapper file generated for DDR3 SDRAM Controller with UniPHY fail to compile in Quartus II software version 11.0? |
| Is QDRII SRAM Controller supported for Stratix III and Stratix IV devices? |
| [Internal] Does the Arria V hard memory controller support RLDRAM II and QDRII / II+? |
| Why do I get an error in the DDR3 with UniPHY memory controller when I uncheck the "Enable Reordering" check box under the Controller Settings tab? |
| Why do I always see read capture timing failure in one of the DDR2/DDR3 SDRAM UniPHY based memory controllers when I have multiple instantiations of DDR2/DDR3 SDRAM UniPHY based memory controller in my design? |
| Critical Warning: Pin mem_clk[0] must have its Cyclone IV E Input Delay from Pin to Internal Cells set to 1 |
| What does "starvation limit for each command" option mean in DDR2 SDRAM and DDR3 SDRAM UniPHY and Altmemphy based controller? |
| What are controller-scheduled autocorrections? |
| Why do I get a hold time violation when compiling my Stratix IV DDR3 SDRAM UniPHY based controller design in the Quartus II software version 11.0SP1? |
| SEVERE: An error occurred while running script "::emif_cal_dbg::odt_cal::run_odt_cal_callback |
| Critical Warning(16643): Found IO_STANDARD assignments found for "ref_clk" pin with multiple values. Using value: "LVDS" |
| Error: Execution of command "{<quartus_installation>/nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed |
| Error Occurs When 256-Character
Limit Exceeded on Windows Systems |
| NativeLink Simulation of DDR2, DDR3,
and LPDDR2 Interfaces Fails for ModelSim AE and ModelSim SE |
| SoC Designs With HPS Memory Interface
and FPGA Memory Controller on Cyclone V Devices Can Encounter Error |
| Is there any issue with DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM High Performance controller II in Arria II GX devices which may cause hardware failure? |
| Why is my DDR3 hard memory controller ODT not toggling? |
| Why do I get error message when I change IO termination value with UniPHY memory controller ? |
| How do I set the DDR3 UniPHY memory controller timing parameters from the External Memory vendor DDR3 datasheet ? |
| Internal Error: Sub-system: ASMIO, File: /quartus/comp/asmio/asmio_dqs_s5.cpp, Line: 2330found_oct_hr_clk ^ found_hr_clk_in |
| Error: add_fileset_file: No such file C:/<temp directory>/qsys/<UniPHY core>_p0_sequencer_rom.hex |
| How can I change the test loop number of the UniPHY example driver ? |
| Are there any additional layout guidleines for UniPHY based DDR3 controller other than the information given in the External Memory Interface Handbook? |
| How do I access the UniPHY CSR registers? |
| Why do I see the drv_status_fail bit assert when I simulate the LPDDR2 example design in Skip Calibration mode? |
| Will local_rdata_valid be asserted when DQS edge is missing due to OCT timing issue reported in solution rd01212009_111? |
| Why did I get Fitter error during compilation when I set ALTMEMPHY wrapper as top level project file? |
| Critical Warning:write pin list has a malformed argument passing from Tcl script. The write assumption verification function is disabled because a complete and proper list is required. |
| Cyclone V GT and Cyclone V E are not appear in the External Memory Interface Spec Estimator |
| Is a board trace model required for UniPHY-based Controller? |
| Group Mask Settings in EMIF Debug
Toolkit Not Applied During Recalibration |
| IP Generation Fails When Both Efficiency
Monitor and Ping Pong PHY Enabled |
| Internal Error in Chip Planner/LogicLock
during EMIF/PHYLite Compilation |
| LPDDR2 GUI Mismatch for Mode Register
2 |
| VCS/VCSMX May Crash When Compiling
Designs With EMIF Simulation Models |
| UniPHY CSR Ports Not Functioning
Correctly for External Memory Interfaces |
| LPDDR2 Designs Using Hard Memory
Interface on Cyclone V Devices Fail to Compile in NCSim and VCS
MX |
| EMIF Debug Toolkit Reports Margin
Larger than Bit Period |
| Critical Warning Mentioning ClockTransfers May Occur During Fitter Phase |
| Address and Command Leveling May
Cause Intermittent Calibration Failures in DDR4 External Memory
Interfaces |
| Why is my Stratix read DQS signal is stuck at an incorrect phase shift? |
| Are there any known issues with "Non-Leveling" UniPHY based DDR3 SDRAM Controller in Quartus II software versions 10.0 and 10.0SP1? |
| Error: Quartus II 64-Bit TimeQuest Timing Analyzer was unsuccessful |
| Critical Warning: Could not find pin of type cmd_pins from pattern
Failed to find PLL clock for pins |
| No Link to the External Memory Interface
Handbook from Wizard |
| What information is contained in the altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_instr.tr file? |
| How do I modify the UniPHY example driver to run continuously? |
| Why does mem_cke signal toggle when I assert local_self_rfsh_req signal on DDR3 SDRAM UniPHY based memory controller? |
| Why is mem_ck[0](n) assigned as differential pair for mem_ck[0] instead of mem_ck_n[0]? |
| Why are there duplicates for the differential signals in the Pin Planner after I run the &lt;variation name&gt;_pin_assignments.tcl file? |
| Critical Warning (308019): (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. |
| What is a possible cause of a DDR4 operational failure after upgrading to the Intel® Quartus® Prime Pro Edition software version 18.1? |
| Why do the debug toolkits print additional debug messages or stop printing messages in other cases? |
| Arria 10 IP with OCT Block May FailSimulation with Questa Advanced Simulator |
| 34-Ohm Parallel Termination Not
Supported for Arria 10 Devices |
| Measured Driver Margins May Be Smaller
than Expected |
| Automatic Upgrade of EMIF IP from 14.1 to 15.1 Does Not Work Correctly |
| Inconsistent Ordering of Local Memory
Addresses in Example Design |
| LRDIMM Support Not Available in
Version 12.1 |
| Error Message Citing Different I/O
Standards for DQ I/O and DQS I/O Pins |
| Quartus II Software v13.0 SP1 Does
Not Recognize Some IP Core Changes From 13.0 |
| DDR3L Designs on Stratix V ES Devices
May Fail in Assembler |
| Designs Targeting Stratix V ES Devices
May Fail Timing in TimeQuest |
| Half Rate Bridge Not Supported in
Simulation |
| Need to Manually Connect Memory
Model |
| Efficiency Monitor Latency Values
Are Incorrect for DDR2 and DDR3 SDRAM Controller with UniPHY and
RLDRAM II Controller with UniPHY |
| Memory Controller Uses 1T Memory
Timing |
| UniPHY IP Generation for External
Memory Interfaces Fails if the Quartus II Installation Path Contains
a Space |
| VHDL-Generated Fileset Can Encounter
Synthesis Problems for UniPHY External Memory Interfaces |
| ECC Registers Not Accessible from
Controller Register Map |
| ECC Interrupt Function Not On by
Default |
| ECC and CSR Designs Fail Timing |
| Error Migrating Design from 11.0
to 11.0 SP1 for DDR2 and DDR3 SDRAM Controller with UniPHY |
| VCS-MX Simulation with Simulation
Script vcsmx_setup.sh Fails at 0ns |
| SOPC Builder Issues Erroneous Error
Message |
| Memory Timing Violation During Activate
Read Auto-Precharge to Refresh/Activate |
| Generate Simulation Model Option
Gets Disabled |
| Error Message When Recompiling a
Project |
| Rule Violation Warnings During Compilation |
| Partitioned Design Compilation Error |
| Memory Preset Parameters Do Not
get Updated |
| Address Mirroring Not Supported
by Memory Simulation Model |
| Failure to Regenerate 9.0 Designs
in Silent Mode |
| Using Merging Feature |
| Wrong Default Value |
| DDR Controller Designs in AFI Mode
with Memory Burst Length of 2 Fail in Simulation |
| Postamble Calibration Scheme in
Sequencer Violates Timing |
| Generate Simulation Model Option
Gets Disabled |
| Simulating with the NCSim Software |
| VHDL Simulation Fails When DDR CAS
Latency 2.0 or 2.5 Is Selected |
| SOPC Builder Does Not Recognize
Decimal Points |
| Incorrect Multiple Port Address
Width |
| Invalid Maximum Avalon-MM burst
length Value Causes Simulation Failure |
| For V-series Families, VHDL is Not
Supported When Read DQS Tracking is Enabled |
| Fitter Error Occurs if Pin-Assignment
TCL File Omitted During Compilation of MAX 10 EMIF IP |
| EMIF Toolkit Will Not Link to Projects
Containing In-System Memory Editor |
| All Devices in Multirank Designs
Must Enter and Exit Self-Refresh at the Same Time |
| Nios II-Based Sequencer for RLDRAM
II Requires a Burst Length of 8 |
| Error May Occur in EMIF VHDL Simulation
with Riviera-PRO |
| User Refresh Limitation in Arria
V and Cyclone V Hard Memory Interface |
| UniPHY-based EMIF is Not Supported on Ubuntu |
| Simulation Failure for QDR-IV Interfaces
with ModelSim-AE on Arria 10 Devices |
| Example Driver Limitation for DDR,
DDR2, and DDR3 Controllers with ALTMEMPHY |
| Possible Simulation Failure with
Arria 10 Devices on Versions 14.1 and 14.1.1 |
| No-Fit in DDR3 Interfaces Due to
mem_ck Assignments |
| DDR3 Recovery Failures on Stratix
V Devices |
| Error Occurs When Generating RLDRAM
3 IP Core With PLL Sharing and EMIF On-Chip Debug Toolkit |
| Low Speed DDR2 Fails Calibration
on Cyclone V Devices |
| Using Burst Merging Feature for
DDR2 and DDR3 SDRAM Controller with UniPHY |
| Memory Controller Returns Wrong
Data |
| Warning Messages Reporting Ignored
SDC Constraints |
| For DDR3 SDRAM Controller with UniPHY
and DDR3 SDRAM Controller with ALTMEMPHY IP, Devices Faster than
533MHz Require Manual Derating |
| VHDL Example Driver Fails in Simulation |
| DQS Clock Buffer Location for QDR
II and QDR II+ SRAM Controller with UniPHY and RLDRAM II Controller
with UniPHY |
| Reset Synchronizer for UniPHY External
Memory Interfaces May Cause Design to Fail Timing when generated
in SOPC Builder or Qsys |
| Example Design Can Fail For Certain
Parameterizations of QDR II and QDR II+ SRAM Controller with UniPHY
and DDR2 and DDR3 SDRAM Controller with UniPHY |
| System Timestamp Mismatch Warning
Message |
| ODT Launches Off System Clock |
| Incorrect IP Functional Simulation
Model for QDR II and QDR II+ SRAM Controller with UniPHY |
| In DDR2 and DDR3 SDRAM Controller
with UniPHY, Selecting VHDL Gives a Verilog HDL IP Core |
| Global Signal Assignments for UniPHY
External Memory Interfaces Not Applied |
| Why do I see the incorrect read latency from eSRAM Intel® Stratix® 10 FPGA IP simulation model ? |
| What is the Arria II GX device DQS Phase Shift Error specification? |
| Can Half-Rate DDR or DDR2 Altmemphy Datapaths be interleaved in Stratix III and Stratix IV devices? |
| Why is the width of DDR3 Avalon interface signal "local_rdata_error" 4 bits? |
| Why can't I generate a DQS phase shift other than 90 degrees in Stratix devices using Quartus II version 4.2? |
| Error (332000): ERROR: Argument "node_object" is an object filter that matches no objects. Specify one matches only one object |
| Is there any known issue when using altdq_dqs megafunction as RLDRAMII mode in Quartus II 11.1SP2? |
| Can the Quartus II EMIF Debug Toolkit be used to debug Arria 10 HPS EMIF IP ? |
| Why do I get BSP generation errors when the SDRAM controller efficiency monitor is enabled? |
| Why must I connect PLL input to a dedicated clock input pin for ALTMEMPHY based memory controller design? |
| Warning (307026): DDR3-SDRAM pin mem_dqs_to_and_from_the_uniphy_ddr3_0[0] must be fed by an OUTPUT_PHASE_ALIGNMENT WYSIWYG with either a 90, 72, 108, degree phase shift |
| How should I determine value of chip bits for Altera High Performance Memory Controller II with multiple chip select? |
| Critical Warning: Memory depth (**) in the design file differs from memory depth (**) in the Memory Initialization File |
| Why do I get the error "Nios II generation failed, input clock is unknown or set to 0" in Qsys when generating my project in Linux? |
| Which pin assignment guideline should I use for QDR II SRAM with read latency of 1.5? |
| Warning: Ignored filter at {variable name}_phy_ddr_pins.tcl(965):{variable name}_phy:*|* could not be matched with a keeper |
| External Memory Interface Handbook: Known Issues |
| Warning: (vsim-3829) ./../altera_emif_arch_nf_181/sim/mem_array_abphy.sv(1257): Non-existent associative array entry. Returning default value. |
| Why doesn’t the Intel® Arria® 10 EMIF Debug Toolkit report the AC Calibration Margin? |
| Why doesn't the Intel® Stratix®10 MX HBM2 controller assert the AXI RVALID signal until the AXI RREADY is asserted from the user interface? |
| What I/O standard setting should be used for the DDR4 alert_n signal? |
| Why does the Intel® Stratix® 10 EMIF Toolkit report DQS Enable Calibration failure? |
| Why doesn’t the Intel® MAX® 10 DDR2 mem_odt signal toggle during calibration in both the RTL simulation and in hardware operation? |
| Why I can’t find Hard PHY and Soft Controller in Cyclone® 10 External Memory Interfaces IP? |
| Error(18948): Error message received from device: Detected internal error. Contact Intel Applications for further assistance. (Subcode 0x002D, Info 0x00000000, Location 0x00019000) |
| Internal Error: Sub-system: AMM, File: /quartus/db/amm/amm_atom_mod_util_impl.cpp, Line: 2199 |
| Warning(16817): Verilog HDL warning at iopll.v(30): overwriting previous definition of iopll module |
| VCS MX Fails in VHDL Simulation
of Arria 10 DDR4 Interface |
| Data Inversion Feature Not Supported
for QDR-IV on Arria 10 Devices |
| Board Skew Analysis Is Incorrect
for Arria V and Cyclone V Devices |
| QDR II and RLDRAM II Interfaces
May Not Close Timing on Arria V Devices |
| Output Pins May Toggle Incorrectly
for EMIF Interfaces on Certain Stratix V Devices |
| Possible Timing Problems With Quarter-Rate
DDR3 on Arria V |
| Simulation With Riviera-PRO May
Fail to Initialize Under Certain Conditions |
| Why does Timequest Report DDR not display the timing margin results of slave interfaces for UniPHY memory interface IP? |
| Does DDR3 SDRAM and DDR2 SDRAM Altmemphy and UniPHY based controller with Error Correction Coding (ECC) enabled support partial write for DIMMs without DM pins? |
| How can I access the Hard Controller Register Map of the UniPHY-based hard memory controller? |
| Is there an issue with DOFF_N pin behaviour in QDR II/+ SRAM UniPHY Megafunction? |
| Why simulation failed in ALTMEMPHY when PLL Reference Frequency is set to decimal point value? |
| Possible Error When Simulating EMIF
Designs in VHDL Using ModelSIM AE |
| Incorrect IP Functional Simulation
Model for RLDRAM II Controller with UniPHY |
| Fitter Error Occurs When Read DQS
Tracking is Enabled |
| VCS Simulation Fails and Reports
that Module was Previously Declared |
| Efficiency Monitor Statistics Incorrect
for Initial Sample in DDR2 and DDR3 SDRAM Controller with UniPHY
and RLDRAM II Controller with UniPHY |
| Simulation Fails for Memory Additive
CAS Latency Settings > 0 |
| ModelSim Waveform Viewer for UniPHY
External Memory Interfaces Shows Only clk and reset Signals |
| Error Related to Incorrect Syntax
of Type Conversion |
| SOPC Builder and Qsys Do Not Support
Full-Rate DDR with HPC I in Simulation |
| Erroneous Timing Failures in Designs
Containing Both UniPHY and ALTMEMPHY Instantiations for External
Memory Interfaces |
| UniPHY EMIF Toolkit Reports Narrow
Data Valid Window |
| Error Occurs When Running Simulation
Example Design in ModelSim or Riviera-PRO |
| Pin Planner HDL Syntax Error |
| Power-Down Entry Command Timing
Violation |
| Cyclone III Speed Grade Support
for Full-Rate DDR2 SDRAM Memory Specification |
| DQS and DQSn Signals Generate Extra
Pulse |
| Refresh to Precharge Command Timing
Violation |
| Timing Violation In Half-Rate Bridge
Enabled Designs |
| Designs with Eight Chip Selects
Fail Compilation |
| Half-Rate Clock Not Connected When
Clock Sharing is Enabled |
| CSR Address 0×005 and 0×006 Contents
Cannot be Accessed |
| RTL Simulation May Fail When Dedicated
Memory Clock Outputs Are Selected |
| Memory Presets Contain Some Incorrect
Memory Timing Parameters |
| Gate Level Simulation Fails |
| Designs with Error Correction Coding
(ECC) Do Not Work After Subsequent Reset |
| Unexpected Timing Results in Design
With Both ALTMEMPHY and UniPHY |
| Simulating with the VCS Simulator |
| Segmentation Fault During Elaboration
with ModelSim SE |
| Compilation Failure with UniPHY
Cores Targeting Arria V and Cyclone V |
| Error When Simulating DDR3 with
Ping Pong PHY Using VHDL and ModelSim |
| Calibration Error Associated With
Qsys Simulation Model Settings |
| Prefitter Not Instantiating io_clock_divider
and DQSLB when DQSLB has No Associated EMIF Pins |
| Altera QDR II Memory Model Behaves
Differently Than Other Vendors’ Memory Models During Concurrent
Transactions |
| Inefficient Memory Transactions
For Quarter-rate Designs |
| Possible Calibration Failure on
Arria 10 10AX115 or 10AX066, ES or ES2 Devices |
| Difficult Timing Closure for QDR-IV
Interfaces on Arria 10 Devices |
| EMIF Toolkit Will Not Link to Designs
Created in Qsys |
| Internal Error when using memory interface toolkit application in QII V12.1 |
| Error: libbytestream.so ELF 32 class not present |
| Mimic Path Incorrectly Placed |
|
SOPC Builder Not Supported for DDR SDRAM Controller with ALTMEMPHY |
| For DDR2 and DDR3 SDRAM Controller
with UniPHY, SOPC Builder Designs Suffer Low Efficiency |
| SOPC Builder-generated Systems Cannot
Serve as Top-Level Design for UniPHY External Memory Interfaces |
| Conduit Error Messages Displayed
in Qsys for UniPHY External Memory Interfaces |
| Warning: Ignored Global Signal option assignment from source signal "PLL output clock name" to destination signal "name"|dll_wys_m -- destination cannot use global signals |
| Warning: On-chip termination control block "name" parameter enable_parallel_termination changed to true |
| Simulation Error QDR II and QDR
II+ SRAM Controller with UniPHY |
| Calibration Failure for QDR II and
QDR II+ SRAM Controller with UniPHY and RLDRAM II Controller with
UniPHY in Earlier Versions |
| Is there a known issue with timing constraints generated by RLDRAMII UniPHY based IP in Quartus II software version 11.0SP1? |
| Is there an issue with DDR2/DDR3 SDRAM High Performance Contoller II with local to memory address mapping? |
| Error: Can't Find the Clock Output
Pins. Stop. |
| –18 Presets Give Errors for RLDRAM
II Controller with UniPHY |
| Incorrect Clock Uncertainty in UniPHY
External Memory Interfaces |
| BSF File Not Generated for UniPHY
External Memory Interfaces |
| Selecting VHDL for QDR II and QDR
II+ SRAM Controller with UniPHY or RLDRAM II Controller with UniPHY
Gives a Verilog HDL IP Core |
| Compilation Fails for UniPHY External
Memory Interfaces if Synthesis Fileset is Mixed with Example Project
Files |
| pin_assignments.tcl Contains Incorrect
Pin Names in Qsys Systems |
| Compilation of a UniPHY Example
Design Can Produce Warnings for UniPHY External Memory Interfaces |
| DDR3 ODT Fails in Simulation with
Denali for DDR2 and DDR3 SDRAM Controller with UniPHY and DDR3 SDRAM
Controller with ALTMEMPHY IP |
| For DDR2 and DDR3 SDRAM Controller
with UniPHY, EMIF Toolkit Reports Incorrect CAS Latency for 10.1
IP Opened in 11.0 |
| Unable to Directly Recompile Quartus
II version 10.1 Design for UniPHY External Memory Interfaces in
Quartus II version 11.0 |
| How to Use UniPHY-based Memory IP
with SOPC Builder |
| Why do I see the mem_reset_n signal is toggling multiple times at the first assertion in skip calibration mode simulation? |
| Error: Cannot find sequencer.elf |
| Why does the PHYLite IP example design fail during the Intel® Quartus® Prime fitter when using OCT with calibration? |
| Is there a flow to pre-initialize the memory content of the Intel® Stratix® 10 MX High Bandwidth Memory (HBM2) for simulation? |
| Is there any issue with power down request in DDR2 SDRAM in Quartus II software version 9.0SP2 and older? |
| Why is the single bit error count reported by the UniPHY High Performance Controller II IP higher than expected when auto-correction is enabled? |
| Why do I see timing violations for the altera_reserved_tck signal when using DDR3 SDRAM controller with UniPHY? |
| How can I speed up the simulation for AFI based DDR2 SDRAM High Performance controller and DDR3 SDRAM High Performance controller without leveling turned ON? |
| Cannot find PLL settings that allow for truncation-free problems in TimeQuest |
| Are there any known problems with the Intel® Stratix® 10 DDR4 Ping Pong PHY example design? |
| Why is there a mismatch on the write and read data between the AXI bus interface and the Intel® Stratix® 10 MX HBM2 simulation model messages during simulation? |
| How are the Intel® Stratix® 10 DDR4 IP chip select signals mapped for the top and bottom memory devices in a clamshell topology? |
| Why does the EMIF Debug Toolkit report that the Intel® Stratix® 10 DDR4 CKE*, ODT*, and RESET signals are uncalibrated? |
| How do I resolve IO_AUX and RST_SRC_ID fitter errors when the Quartus Prime project contains Arria 10 External Memory Interfaces IP ? |
| How do I modify the Arria 10 PCI development kit DDR4 External Memory Interface example design project to have a smaller data width than 72 bits ? |
| What may cause the Intel® Stratix® 10 DDR4 IP to not return read data promptly prior to a long idle time? |
| What may cause the Intel® Stratix® 10 DDR4 IP to execute an additional refresh after a self-refresh exit? |
| What are the EMIF frequency specifications for low power Intel Arria 10 FPGA devices ? |
| Error: The connection to the hardware drivers could not be established |
| Can the Intel® Stratix® 10 HBM2 efficiency monitor test pattern run in an infinite loop? |
| What can cause memory test data errors to occur when using the Intel® Stratix® 10 FPGA DDR4 EMIF IP configured for 16Gb size DDR4 memory devices? |
| What may cause the Intel® Stratix® 10 DDR4 IP to violate the Exit Power Down to Refresh Minimum Delay (tXP)? |
| Why does the Intel® Stratix® 10 External Memory Interfaces DDR4 IP show minimum pulse violations on the wf_clk clocks in the Intel Quartus® Prime timing analyzer? |
| How can the generation of the iossm_bf_cpu_cpu.tr file be disabled when simulating the Intel® Stratix® 10 DDR4 IP? |
| ERROR: iossm_bf_cpu_cpu_test_bench/ihp_read is 'x' |
| Warning: adfa.emif_s10_0.col_if.colmaster: package require -exact qsys 16.0 must be before any commands in the package |
| Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_netlist_modifier.cpp, Line: 1213 |
| External Memory Interfaces Targeting
Some Stratix V Devices Do Not Function Correctly in Hardware |
| Warning Messages About afi_rdata_valid,
afi_rdata_en, afi_rdata_en_full |
| Example Designs for UniPHY External
Memory Interfaces May Not Compile for IP Cores from Earlier Versions |
| Does the Intel® Quartus® Prime Pro software generate IBIS models for Intel Stratix® 10 MX device UIB_PLL_REF_CLK and CLK_ESRAM pins? |
| How can the mem_clk delay steps of the Intel® UniPHY IP controllers be changed by the ECO flow? |
| Why can’t four DDR4 x72 DIMM interfaces be implemented in the Intel® Stratix® 10 MX FPGAs? |
| Error(16282): Two or more external memory interface (EMIF) IP cores in the same column use different calibration routines. |
| Why does the EMIF calibration hang when both an Intel® Arria® 10 External Memory Interfaces IP and an Intel Arria 10 PHYLite IP are placed in the same I/O column? |
| *** Fatal Error: Segment Violation: faulting address=0x30 when compiling a project with the Intel® Arria® 10 PHYLite IP |
| How does the transaction count operate after grant moves to the next master when using the Intel® Stratix®10 MX HBM2 controller with the AXI* Switch? |
| What are the calibration sequences for the Intel® Stratix® 10 EMIF IP? |
| Warning: Ignored Maximum Fan-Out assignment |
| What EMIF Toolkit features are not supported for Intel® Stratix® 10 FPGAs in Intel Quartus® Prime Pro Edition software? |
| Error(19433): Transfer between periphery and DSP or RAM <signal_path> will make timing transfer impossible. |
| Are there timing updates for the Intel® Stratix® 10 MX ES FPGA devices? |
| Why does the PowerPlay Early Power Estimator (EPE) show incorrect number of Hard Memory Controller (HMC) when the EPE imports the PowerPlay Early Power Estimator (.csv) file? |
| Why do I see hold time violations in Core path under "Report DDR" timing report of DDR3 SDRAM Controller with UniPHY when implementing it in HardCopy devices? |
| Error in Graphical Display of DQ
Calibration Margin in EMIF Toolkit for DDR2 and DDR3 SDRAM Controller
with UniPHY |
| Does the Intel® Arria® 10 DDR4 IP support 3-dimensional stack (3DS) memory? |
| Why does the interface 1 port simulate incorrectly when the abstract phy simulation model is used in the Intel® Arria® 10 DDR4 Ping Pong PHY IP? |
| How do I fix hold timing violations between the c2p_write_clk and the pll_write_clk for a Stratix V DDR3 design? |
| Why Arria10 EMIF asserts mmr_readdata_valid in calibration? |
| What is the minimum pulse width required for the Arria 10 EMIF IP global_reset_n signal ? |
| How can the Arria 10 EMIF Traffic Generator be set for infinite loop test? |
| Why are the Arria 10 DDR4 MMR signals (e.g. mmr_slave_readdatavalid_0) toggling even though there are no user read request? |
| What is the maximum burst count for the Arria 10 External Memory Interface IP? |
| Does the Stratix 10 hard memory controller support 2T timing for the address/command bus? |
| Does Intel® Stratix® 10 FPGA External Memory Interface IP require Periodic OCT Re-Calibration? |
| Why does the awready signal from the AXI* Switch toggle when using Intel® Stratix® 10 MX HBM2 controller? |
| Why does the Intel® Arria® 10 DDR4 IP not correct an ECC error? |
| Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. |
| Why can’t the Intel® Arria® 10 DDR3 IP exit self-refresh mode? |
| Internal Error: Sub-system: SIN, File: /quartus/tsm/sin/sin_micro_tnodes_dag.cpp, Line: 978 |
| Critical Warning: DDR Timing requirements not met |
| Why does the local_cal_success go high but local_init_done stay low during RTL simulation for the hard memory controller? |
| Why is the Intel® Arria® 10 PHYLite IP core interface_locked signal not asserted? |
| How can the buffer size of the Intel® Arria® 10 External Memory Interface (EMIF) IP be controlled to reduce the RAM blocks usage in the FPGA device? |
| Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_hardware_reader_nf_emif_131_impl.cpp, Line: 1905 |
| Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column. |
| Why doesn't the EMIF Spec Estimator show support for DDR4 SODIMM memory topology for quad rank in a 2 slot dual rank configuration for the Intel® Arria® 10 FPGA? |
| Error(14996): The Fitter failed to find a legal placement for all periphery components |
| Why does the Intel® Stratix® 10 DDR3 IP fail calibration when upgrading to Intel Quartus® Prime software version 17.1.2 or later? |
| Do the Intel® Stratix® 10 FPGA devices support QDR-IV at 1067 MHz using the -2 speed grade parts? |
| Why are my Instances and Details fields in the Intel® Quartus® Prime software System Console, Toolkit Explorer tab empty? |
| How can an infinite test duration be assigned in the Intel® Agilex® TG2 Toolkit? |
| Reference clock network for 12 tiles is not currently supported |
| Error (332000): can't read "pll_ref_clock": no such variable |
| How can the read data path read_capture_clk signal of the Intel® UniPHY IP be probed on a test pin by using ECO? |
| Warning(332035): No clocks found on or feeding the specified source node |
| Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_connection_manager_impl.cpp, Line: 426 |
| What is the recommended termination guideline for mem_reset_n when using DDR3 SDRAM controller with UniPHY? |
| Why do I see random read errors when using the ALTDQ_DQS2 megafunction? |
| Error: Export Address/Command parity error indicator cannot be used if Addr/CMD parity latency is disabled. Addr/CMD parity latency is controlled in the Mode Register Settings section of the Memory tab (advanced setting) |
| Error(20959): Module instance "emif_fm_hps_0|emif_fm_hps_0|arch|arch_inst|pll_inst|pll_inst", which is a tennm_iopll primitive, has unexpected connections on port LOCK. |
| Can the Intel® Arria® 10 PHYLite and the Intel Stratix® 10 PHYLite IPs support two x4 DQ/DQS groups in one I/O lane? |
| What temperature is the Intel® Stratix® 10 MX Device HBM2 memory CATTRIP sensor activated? |
| How can the memory capacity of a HiLo board fitted with Micron* parts be determined? |
| Error: Simulation initialization failed. |
| Why is the Run Driver Margins option not available in the EMIF Debug Toolkit when targeting the Intel® Agilex® FPGA devices? |
| Can the Intel® Agilex® EMIF Debug Toolkit report the address/command margins? |
| How can the EMIF Debug Toolkit support multiple Intel® Agilex® EMIF Interfaces? |
| Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)) |
| Does the Intel® Agilex® DDR4 IP support Abstract PHY simulation? |
| Can the Intel® Agilex® EMIF Debug Toolkit support interfaces in two different I/O rows? |
| Internal Error: Sub-system: ASMIO, File: /quartus/comp/asmio/asmio_reg.cpp, Line: 6596 |
| Why does the Intel® Stratix® 10 HBM2 IP calibration success signal stay low at Tj less than 0°C ? |
| Why is the read data value incorrect for the DQS input delay when using the Dynamic Reconfiguration mode in the Intel® Arria® 10 PHYLite IP? |
| How do I achieve higher clock rates in Cyclone III full-rate DDR2 SDRAM High Performance Controller II in Quartus II software version 9.1 and beyond? |
| Error(13149): EMIF/PHYLite systems sharing a PLL reference clock do not have identical reset inputs for following io_aux atoms |
| Why is the parameter “Use core PLL reference clock connection” not available in the PHYLite IP Parameter Editor? |
| Why does the Hybrid Memory Cube example design not generate in Quartus Prime Pro 17.1 when configured with 8 Lanes ? |
| Error (10198): Verilog HDL error at phylite_io_bufs.sv(1078): part-select direction is opposite from prefix index direction |
| Why can't the interface clock frequency be set to a value between 137.5MHz to 149.9MHz for the Intel® Arria® 10 PHYLite IP when using quarter rate mode? |
| How does temperature affect the Intel® Stratix® 10 HBM2 interface efficiency and bandwidth? |
| Can the slew rate be changed in the EMIF IP for Intel® Agilex® FPGA devices? |
| Error(20714): OCT "emif_fm_0_oct_oct_rzqin~pad" requests I/O standard "1.2-V POD" and Rt resistance "Parallel 50 Ohm with Calibration", but this I/O standard only supports Rt resistance ""Parallel 60 Ohm with Calibration". |
| Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column |
| Why doesn’t the Intel® Cyclone® V device part number get assigned to the generated Intel UniPHY® example design? |
| Can the Intel® Agilex® Hard Processor System (HPS) DDR4 IP support ECC? |
| Error (175001): Could not place HPHY |
| Why does the Intel® Stratix® 10 MX device fail configuration? |
| Error (175006): There is no routing connectivity between the clock tree and destination UFIND4H_UIB |
| Why does the Intel® Arria® 10 PHYLite IP fail simulation when the data configuration is set to “Differential”? |
| Are there any additional PCB layout recommendations when using twin-die DDR4 memory devices ? |
| Why does the Intel® Cyclone® 10 DDR3 IP emif_usr_clk frequency simulate inaccurately? |
| Why does the FPGA part number change when generating the UniPHY EMIF example designs? |
| Why is 0mA current seen on VCCIO_UIB and VCCM_WORD in the Intel® Quartus® Prime Power Analyzer results when using an HBM2 interface? |
| Error in Board Settings GUI |
英特尔® Agilex® FPGA EMIF IP 概述
英特尔Stratix® 10、英特尔® Arria® 10和英特尔® Cylcone® 10 EMIF IP 用户指南 (原 EMIF 手册卷 1-3)