Possible Causes for PLL Loss of Lock

A phase-locked loop (PLL) can lose lock for a number of reasons. The following are some common causes for the PLL to lose lock. If the explanation of these causes do not resolve your issue, submit a service request to mySupport, Altera's technical online support system.

Jitter on PLL input clock is out of specification

Excessive jitter on the input clock can cause the PLL to lose lock. For PLL input jitter specification, refer to the DC and Switching Characteristics chapter in the device family handbook.

Since the PLL acts as a low-pass filter, you can use it to filter input jitter as well. The programmable bandwidth feature allows you to control the low-pass response characteristics. To filter higher frequency jitter, use a low bandwidth setting. To track jitter, use a high bandwidth setting. Refer to the PLL chapter in the device family handbook to check whether the PLL in that device supports the programmable bandwidth feature.

To check whether jitter is a problem, compare your input clock’s jitter characteristics (in the frequency domain) with the PLL’s bandwidth (reported in the Quartus® Prime or Quartus II PLL Summary Report file). If your jitter frequency is within the bandwidth or falls near the edge of the bandwidth, it could be coupling through or being slightly amplified (due to jitter peaking).

Simultaneous switching noise (SSN)

Excessive switching noise on the clock inputs of the PLL could cause the PLL to lose lock. Switching noise on the inputs is a form of deterministic jitter that is subject to the input jitter specification shown in the device family data sheet.

Power supply noise

Excessive noise on the VCCA plane can cause high output jitter and possible loss of lock. VCCA is subject to the same requirements (+/- 5%) as the other device power supplies. Again, you can use the PLL bandwidth setting to suppress some of the output jitter. Since VCCA powers the voltage controlled oscillator (VCO), noise on this supply could cause the VCO output frequency to fluctuate and cause jitter. A low bandwidth causes the loop to respond slower to the noise being injected by the VCO. In turn, it cannot adjust for this noise and counteract it. A high bandwidth, on the other hand, allows the loop to respond quickly to the noise and compensate for it.

Input clock stops/glitches or there is a sudden phase change

A glitch or stopping of the input clock to the PLL could cause the PLL to lose lock. The PLL operates by using a feedback loop to track a reference clock. If the reference clock stops, the PLL no longer has a signal to track. If there is a sudden, drastic phase change of the input clock, the PLL may not be able to react quickly enough to maintain lock.

PLL is reset

Asserting the areset or pllena ports of the PLL causes it to lose lock. These ports reset all the PLL counters and reset the VCO to its nominal value.

An attempt has been made to reconfigure the PLL

Once the scanwrite port is asserted, the PLL scan chain is uploaded to the actual counters. The PLL could lose lock during or after PLL reconfiguration if the M counter, N counter, or phase shift settings have changed during the reconfiguration process. Changes to the post-scale counters do not affect the PLL lock signal.

Stratix® or Cyclone® PLLs lose lock at low temperatures (< -20C)

This is a known issue. For details, see the Stratix FPGA Errata Sheet or Table 4 -52 in the DC & Switching Characteristics chapter of the Cyclone Device Handbook.

Input clock frequency goes outside the lock range as reported in the Quartus Prime or Quartus II PLL Summary Report file

The input clock frequency must stay within the minimum and maximum lock frequency.

Phase frequency detector (PFD) is disabled using pfdena port

When the PFD is disabled, the loop no longer tracks changes to the input clock. The PLL output continues to toggle at the last frequency but drifts to a lower frequency (or higher, depending on the clock setting). The PLL could lose lock since the output clock phase (and frequency) has drifted outside of the lock window of the PLL.

How the PLL Gains Lock

Upon power up, the PLL VCO's control voltage is set to a voltage slightly above VCCA/2. This corresponds to a certain frequency (generally the mid-point of the VCO operating range). Depending on the PLL input frequency and the M counter setting, the VCO attempts to either increase or decrease in frequency to match the PFD input frequency (which is fIN/N).

How fast the PLL reacts is dependent on the loop settings of the PLL. Once the PLL gains frequency lock, the PFD tries to match the phase of the input clock to the feedback clock. How closely the phase is matched is based on the lock window setting (which is determined by the Quartus Prime or Quartus II software). The lock detect circuitry comes from the PLL loop, which means the clock signals to the PFD are observed to determine if they are close enough in phase (within the lock window setting) for the PLL to be considered locked.