文档 | 发布日期 | Filter | Doc Type Filter | Collections Filter | |
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2019-11-04 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/user-guide | ||
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2019-10-01 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property,altera:development-software | |
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2019-10-22 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
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2019-10-14 | altera:document-type/reference-manual,altera:document-type/user-guide | altera:development-software | ||
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2019-09-30 | altera:content-area/hard-processor-system,altera:content-area/development-kits | altera:document-type/release-notes | altera:intellectual-property,altera:development-software | |
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2019-09-30 | altera:content-area/hard-processor-system,altera:content-area/development-kits | altera:document-type/release-notes | altera:intellectual-property,altera:development-software | |
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2019-10-17 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:development-software | |
10-Gbps Ethernet (10GbE) MAC IP Core Release Notes | 2016-05-02 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
100G Interlaken IP Core Release Notes | 2016-05-02 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | altera:intellectual-property | |
25G Ethernet Design Example User Guide | 2017-11-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
50 Gbps Ethernet IP Core User Guide | 2017-11-07 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
50G Ethernet IP Core Release Notes | 2017-05-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | altera:intellectual-property | |
50G Interlaken IP Core Release Notes | 2016-05-02 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | altera:intellectual-property | |
ALTERA_CORDIC IP Core User Guide | 2017-05-08 | altera:document-type/user-guide | altera:intellectual-property | ||
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller | 2017-09-22 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/app-notes | ||
AN 717: Nios II Gen2 硬件开发教程 | 2014-09-22 | altera:document-type/app-notes | |||
AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines | 2015-05-04 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | ||
AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ) | 2016-05-20 | altera:document-type/app-notes | |||
AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report | 2015-12-18 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property | |
AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report | 2015-11-02 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property | |
AN 770: Partially Reconfiguring a Design on Intel Arria 10 SoC Development Board | 2017-11-06 | altera:document-type/app-notes | altera:development-software | ||
AN 805: Hierarchical Partial Reconfiguration of a Design on Intel Arria 10 SoC Development Board | 2017-11-06 | altera:document-type/app-notes | altera:development-software | ||
AN-720: Simulating the ASMI Block in Your Design | 2015-08-03 | altera:document-type/app-notes | |||
AN-744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices | 2016-04-27 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes,altera:document-type/reference-design | altera:intellectual-property | |
AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report | 2016-12-06 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property | |
AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design | 2015-12-14 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property | |
AN742: PMBus SmartVID Controller Reference Designs | 2017-05-08 | altera:content-area/power-and-thermal-management | altera:document-type/app-notes | ||
AN746: SDI II Triple-Rate Reference Designs for Arria 10 Devices | 2017-05-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property | |
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP) | 2015-11-02 | altera:content-area/pcb-layout-and-packaging | altera:document-type/app-notes | ||
AN756: Altera GPIO to Altera PHYLite Design Implementing Guidelines | 2017-05-08 | altera:document-type/app-notes | |||
AN768: Multi Rate (Up to 12G) SDI II Reference Design for Arria 10 Devices | 2017-05-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property | |
AN793: Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design | 2017-06-13 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes,altera:document-type/design-guides | altera:intellectual-property | |
AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design | 2017-02-01 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property | |
AN795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria 10 Devices | 2017-02-01 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property | |
Altera错误信息寄存器卸载器IP内核用户指南 | 2014-12-15 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property,altera:development-software | |
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes | 2016-10-31 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
Arria 10 FPGA Development Kit User Guide | 2016-05-02 | altera:content-area/development-kits | altera:document-type/user-guide | altera:content-area/recommended-documents | |
Arria 10 FPLL IP Core Release Notes | 2016-10-31 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
Arria 10 Native Fixed Point DSP IP Core User Guide | 2016-06-10 | altera:document-type/user-guide | |||
Arria 10 SoC Virtual Platform User Guide | 2015-09-16 | altera:document-type/user-guide | altera:content-area/recommended-documents | ||
Arria 10 SoC Virtual Platform Version 1.0 Release Notes | 2015-09-04 | altera:document-type/release-notes | |||
Arria 10 Transceiver ATX PLL IP Core Release Notes | 2016-10-31 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
Arria 10 Transceiver CMU PLL IP Core Release Notes | 2016-10-31 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
Arria 10 Transceiver Native PHY IP Core Release Notes | 2016-10-31 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
Configuring Altera FPGAs | 2014-12-15 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/user-guide | ||
High-speed Reed-Solomon IP Core Release Notes | 2017-11-06 | altera:content-area/embedded-memory---dsp | altera:document-type/release-notes | altera:intellectual-property | |
Hybrid Memory Cube Controller Design Example User Guide | 2016-05-02 | altera:content-area/external-memory-interface,altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | ||
Hybrid Memory Cube Controller IP Core Release Notes | 2016-05-02 | altera:content-area/external-memory-interface,altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
Implementing PHYLite in Arria 10 Devices Design Examples | 2017-05-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | ||
Intel Arria 10 Native Floating-Point DSP Intel FPGA IP User Guide | 2017-11-06 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
Intel Arria 10 SoC Secure Boot User Guide | 2017-11-06 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/app-notes | ||
Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe Design Example User Guide | 2017-11-06 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Intel Arria 10 and Intel Cyclone 10 Avalon-ST Hard IP for PCIe Design Example User Guide | 2017-11-06 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Intel Quartus Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization | 2017-11-06 | altera:document-type/user-guide | altera:development-software | ||
Interlaken PHY IP Core Release Notes | 2016-10-31 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
LDPC IP Core User Guide | 2017-11-06 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
Low Latency 100-Gbps Ethernet IP Core Release Notes | 2017-07-07 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | altera:intellectual-property | |
Low Latency 100G Ethernet Design Example User Guide | 2017-11-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes | 2017-07-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | altera:intellectual-property | |
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide | 2017-12-28 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Low Latency 40-Gbps Ethernet IP Core Release Notes | 2017-07-07 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | altera:intellectual-property | |
Low Latency 40G Ethernet Example Design User Guide | 2017-11-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Nios II Embedded Design Suite Release Notes | 2015-06-17 | altera:document-type/release-notes,altera:document-type/design-guides | |||
Other Transceiver IP Cores Product Release Notes | 2016-10-31 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
PowerPlay Early Power Estimator for Arria 10 User Guide | 2016-11-07 | altera:content-area/power-and-thermal-management | altera:document-type/user-guide | ||
Quartus Prime Settings File Reference Manual | 2017-05-08 | altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/clocking,altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/reference-manual | altera:development-software | |
Random Number Generator IP Core User Guide | altera:document-type/user-guide | altera:intellectual-property | |||
SDI Audio IP Cores Release Notes | 2017-05-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
Serial Digital Interface (SDI) IP Core Release Notes | 2017-05-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | ||
SerialLite II IP Core Release Notes | 2017-05-08 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | altera:intellectual-property | |
SmartVID控制器IP内核用户指南 | 2015-05-04 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | ||
Turbo IP Core User Guide | 2015-11-11 | altera:document-type/user-guide | altera:intellectual-property | ||
Vision Processing with the Canny Edge Detection Reference Design | 2015-02-14 | altera:document-type/app-notes | |||
Vision Processing with the Canny Edge Detection Reference Design | 2015-02-14 | altera:document-type/app-notes | |||
Viterbi IP Core User Guide | 2017-11-06 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
混合存储立方体控制器IP内核用户指南 | 2016-05-02 | altera:content-area/external-memory-interface,altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | ||
100G Interlaken Design Example User Guide | 2018-03-22 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
25G Ethernet Intel FPGA IP Release Notes | 2019-07-01 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/release-notes | altera:intellectual-property | |
50G Ethernet Design Example User Guide | 2019-04-03 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
50G Interlaken Design Example User Guide | 2018-03-22 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification | 2018-09-01 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/app-notes | ||
AN 763: Intel Arria 10 SoC Device Design Guidelines | 2019-04-17 | altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/development-kits,altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:intellectual-property,altera:development-software | |
AN 798: Partial Reconfiguration with the Arria 10 HPS | 2017-01-25 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/app-notes,altera:document-type/design-guides | ||
AN 872: Thermal and Power Guidelines: For Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA | 2019-08-30 | altera:content-area/power-and-thermal-management | altera:document-type/app-notes | ||
ASMI Parallel II Intel FPGA IP Core Release Notes | 2018-05-07 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/release-notes | ||
Altera Complete Design Suite Version 14.0 Arria 10 Edition Update Release Notes | 2014-09-01 | altera:document-type/release-notes | altera:development-software | ||
Arria 10 SoC Development Kit User Guide | 2018-08-09 | altera:content-area/development-kits | altera:document-type/user-guide | altera:content-area/recommended-documents | |
Avalon Verification IP Suite: User Guide | 2019-04-03 | altera:content-area/timing-analysis-and-simulation,altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
BCH Intel FPGA IP: User Guide | 2018-11-30 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
Battery Management System Reference Design | 2016-04-02 | altera:document-type/reference-manual | altera:development-software | ||
Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms | 2016-12-13 | altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/embedded-memory---dsp | altera:document-type/app-notes,altera:document-type/design-guides | altera:development-software | |
Differences Among Intel SoC Device Families | 2018-08-22 | altera:content-area/external-memory-interface,altera:content-area/hard-processor-system | altera:document-type/reference-manual,altera:document-type/user-guide | altera:content-area/recommended-documents | |
Embedded Design Handbook | 2018-11-12 | altera:content-area/embedded-memory---dsp | altera:document-type/design-guides,altera:document-type/user-guide | altera:development-software | |
FFT IP Core: User Guide | 2017-11-06 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
FIR II IP Core: User Guide | 2017-11-06 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
Floating-Point IP Cores User Guide | 2016-12-09 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
Guidelines for Developing a Nios II HAL Device Driver | 2015-06-12 | altera:document-type/app-notes,altera:document-type/design-guides | |||
High-speed Reed-Solomon IP Core User Guide | 2017-11-06 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
Intel Accelerator Functional Unit Simulation Environment Quick Start User Guide | 2019-08-05 | altera:content-area/end-applications | altera:document-type/user-guide | ||
Intel Arria 10 Core Fabric and General Purpose I/Os Handbook | 2019-09-06 | altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/clocking,altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp,altera:content-area/power-and-thermal-management | altera:document-type/user-guide | altera:content-area/recommended-documents | |
Intel Arria 10 Hard Processor System Technical Reference Manual | 2019-07-09 | altera:document-type/reference-manual,altera:document-type/user-guide | altera:content-area/recommended-documents | ||
Intel Arria 10 SX Device Errata and Design Recommendations | 2018-10-17 | altera:document-type/errata-sheets | altera:collection/data-sheet,altera:content-area/recommended-documents | ||
Intel Arria 10器件数据表 | 2017-05-08 | altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/clocking,altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp,altera:content-area/power-and-thermal-management | altera:document-type/data-sheets | altera:collection/data-sheet,altera:content-area/recommended-documents | |
Intel Arria 10器件概述 | 2017-05-08 | altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/clocking,altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp,altera:content-area/power-and-thermal-management | altera:document-type/device-overview | altera:collection/data-sheet,altera:content-area/recommended-documents | |
Intel FPGA GPIO IP内核用户指南 | 2017-11-06 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Intel FPGA Software Installation and Licensing Quick Start | 2018-11-26 | altera:document-type/user-guide | altera:development-software | ||
Intel FPGA Voltage Sensor IP Core User Guide | 2018-02-09 | altera:content-area/power-and-thermal-management | altera:document-type/user-guide | altera:intellectual-property | |
Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Data Sheet | 2019-05-30 | altera:content-area/end-applications | altera:document-type/data-sheets | altera:collection/data-sheet | |
Intel Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis | 2018-05-09 | altera:document-type/user-guide | altera:development-software | ||
Intel Quartus Prime Standard Edition Handbook Volume 3 Verification | 2018-05-09 | altera:document-type/user-guide | altera:development-software | ||
Intel SoC FPGA Embedded Development Suite User Guide | 2019-05-16 | altera:content-area/hard-processor-system | altera:document-type/user-guide | altera:intellectual-property,altera:development-software | |
LVDS SERDES Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices | 2019-05-03 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Low Latency 100-Gbps Ethernet IP Core User Guide | 2018-01-03 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Low Latency 40-Gbps Ethernet IP Core User Guide | 2018-01-03 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
NCO IP Core: User Guide | 2017-11-06 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
Native Loopback Accelerator Functional Unit (AFU) User Guide | 2019-08-05 | altera:content-area/end-applications | altera:document-type/user-guide | ||
Networking Interface for Open Programmable Acceleration Engine: Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA | 2019-08-05 | altera:document-type/user-guide | |||
OCT Intel FPGA IP User Guide | 2019-07-03 | altera:content-area/external-memory-interface,altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces | 2017-01-23 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Reed-Solomon II IP Core User Guide | 2016-05-02 | altera:content-area/embedded-memory---dsp | altera:document-type/user-guide | altera:intellectual-property | |
Remote Update Intel FPGA IP Core Release Notes | 2018-05-07 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/release-notes | ||
SerialLite II IP Core User Guide | 2019-01-09 | altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/user-guide | altera:intellectual-property | |
Tandem Motion-Power 48 V Board Reference Manual | 2016-08-01 | altera:document-type/reference-manual | altera:development-software | ||
Unique Chip ID Intel FPGA IP Core Release Notes | 2018-05-07 | altera:content-area/device-configuration-and-remote-system-upgrades | altera:document-type/release-notes | ||
Using Intel Arria 10 SoC FPGA Early I/O Release | 2018-10-11 | altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/i-o-interfaces-protocols-and-signal-integrity | altera:document-type/app-notes | altera:content-area/recommended-documents |
- AN 425: 使用命令行 Jam STAPL 解决方案实现器件编程
- AN 425: 使用命令行 Jam STAPL 解决方案实现器件编程(英语)
- OTN 家族 | 200G P-OTS 任意速率映射器 | TPOC226 (1.0 版,2014 年 3 月,607 KB)
(软硅功能)
- OTN 家族 | 400G 转发器/复用转发器 | TPO516 (1.0 版,2014 年 3 月,469 KB)
(软硅功能)