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Advanced Link Analyzer User Guide 2019-11-04
CPRI Intel FPGA IP User Guide 2019-10-01
Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide 2019-10-22
Intel FPGA Software Installation and Licensing 2019-10-14
Intel SoC FPGA Embedded Development Suite (SoC EDS) Professional Version 19.3 Release Notes 2019-09-30
Intel SoC FPGA Embedded Development Suite (SoC EDS) Standard Version 19.1 Release Notes 2019-09-30
Nios II Processor Reference Guide 2019-10-17
10-Gbps Ethernet (10GbE) MAC IP Core Release Notes 2016-05-02
100G Interlaken IP Core Release Notes 2016-05-02
25G Ethernet Design Example User Guide 2017-11-08
50 Gbps Ethernet IP Core User Guide 2017-11-07
50G Ethernet IP Core Release Notes 2017-05-08
50G Interlaken IP Core Release Notes 2016-05-02
ALTERA_CORDIC IP Core User Guide 2017-05-08
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller 2017-09-22
AN 717： Nios II Gen2 硬件开发教程 2014-09-22
AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines 2015-05-04
AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ) 2016-05-20
AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report 2015-12-18
AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report 2015-11-02
AN 770: Partially Reconfiguring a Design on Intel Arria 10 SoC Development Board 2017-11-06
AN 805: Hierarchical Partial Reconfiguration of a Design on Intel Arria 10 SoC Development Board 2017-11-06
AN-720: Simulating the ASMI Block in Your Design 2015-08-03
AN-744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices 2016-04-27
AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report 2016-12-06
AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design 2015-12-14
AN742: PMBus SmartVID Controller Reference Designs 2017-05-08
AN746: SDI II Triple-Rate Reference Designs for Arria 10 Devices 2017-05-08
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP) 2015-11-02
AN756: Altera GPIO to Altera PHYLite Design Implementing Guidelines 2017-05-08
AN768: Multi Rate (Up to 12G) SDI II Reference Design for Arria 10 Devices 2017-05-08
AN793: Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design 2017-06-13
AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design 2017-02-01
AN795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria 10 Devices 2017-02-01
Altera错误信息寄存器卸载器IP内核用户指南 2014-12-15
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes 2016-10-31
Arria 10 FPGA Development Kit User Guide 2016-05-02
Arria 10 FPLL IP Core Release Notes 2016-10-31
Arria 10 Native Fixed Point DSP IP Core User Guide 2016-06-10
Arria 10 SoC Virtual Platform User Guide 2015-09-16
Arria 10 SoC Virtual Platform Version 1.0 Release Notes 2015-09-04
Arria 10 Transceiver ATX PLL IP Core Release Notes 2016-10-31
Arria 10 Transceiver CMU PLL IP Core Release Notes 2016-10-31
Arria 10 Transceiver Native PHY IP Core Release Notes 2016-10-31
Configuring Altera FPGAs 2014-12-15
High-speed Reed-Solomon IP Core Release Notes 2017-11-06
Hybrid Memory Cube Controller Design Example User Guide 2016-05-02
Hybrid Memory Cube Controller IP Core Release Notes 2016-05-02
Implementing PHYLite in Arria 10 Devices Design Examples 2017-05-08
Intel Arria 10 Native Floating-Point DSP Intel FPGA IP User Guide 2017-11-06
Intel Arria 10 SoC Secure Boot User Guide 2017-11-06
Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe Design Example User Guide 2017-11-06
Intel Arria 10 and Intel Cyclone 10 Avalon-ST Hard IP for PCIe Design Example User Guide 2017-11-06
Intel Quartus Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization 2017-11-06
Interlaken PHY IP Core Release Notes 2016-10-31
LDPC IP Core User Guide 2017-11-06
Low Latency 100-Gbps Ethernet IP Core Release Notes 2017-07-07
Low Latency 100G Ethernet Design Example User Guide 2017-11-08
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes 2017-07-08
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide 2017-12-28
Low Latency 40-Gbps Ethernet IP Core Release Notes 2017-07-07
Low Latency 40G Ethernet Example Design User Guide 2017-11-08
Nios II Embedded Design Suite Release Notes 2015-06-17
Other Transceiver IP Cores Product Release Notes 2016-10-31
PowerPlay Early Power Estimator for Arria 10 User Guide 2016-11-07
Quartus Prime Settings File Reference Manual 2017-05-08
Random Number Generator IP Core User Guide
SDI Audio IP Cores Release Notes 2017-05-08
Serial Digital Interface (SDI) IP Core Release Notes 2017-05-08
SerialLite II IP Core Release Notes 2017-05-08
SmartVID控制器IP内核用户指南 2015-05-04
Turbo IP Core User Guide 2015-11-11
Vision Processing with the Canny Edge Detection Reference Design 2015-02-14
Vision Processing with the Canny Edge Detection Reference Design 2015-02-14
Viterbi IP Core User Guide 2017-11-06
混合存储立方体控制器IP内核用户指南 2016-05-02
100G Interlaken Design Example User Guide 2018-03-22
25G Ethernet Intel FPGA IP Release Notes 2019-07-01
50G Ethernet Design Example User Guide 2019-04-03
50G Interlaken Design Example User Guide 2018-03-22
AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification 2018-09-01
AN 763: Intel Arria 10 SoC Device Design Guidelines 2019-04-17
AN 798: Partial Reconfiguration with the Arria 10 HPS 2017-01-25
AN 872: Thermal and Power Guidelines: For Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA 2019-08-30
ASMI Parallel II Intel FPGA IP Core Release Notes 2018-05-07
Altera Complete Design Suite Version 14.0 Arria 10 Edition Update Release Notes 2014-09-01
Arria 10 SoC Development Kit User Guide 2018-08-09
Avalon Verification IP Suite: User Guide 2019-04-03
BCH Intel FPGA IP: User Guide 2018-11-30
Battery Management System Reference Design 2016-04-02
Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms 2016-12-13
Differences Among Intel SoC Device Families 2018-08-22
Embedded Design Handbook 2018-11-12
FFT IP Core: User Guide 2017-11-06
FIR II IP Core: User Guide 2017-11-06
Floating-Point IP Cores User Guide 2016-12-09
Guidelines for Developing a Nios II HAL Device Driver 2015-06-12
High-speed Reed-Solomon IP Core User Guide 2017-11-06
Intel Accelerator Functional Unit Simulation Environment Quick Start User Guide 2019-08-05
Intel Arria 10 Core Fabric and General Purpose I/Os Handbook 2019-09-06
Intel Arria 10 Hard Processor System Technical Reference Manual 2019-07-09
Intel Arria 10 SX Device Errata and Design Recommendations 2018-10-17
Intel Arria 10器件数据表 2017-05-08
Intel Arria 10器件概述 2017-05-08
Intel FPGA GPIO IP内核用户指南 2017-11-06
Intel FPGA Software Installation and Licensing Quick Start 2018-11-26
Intel FPGA Voltage Sensor IP Core User Guide 2018-02-09
Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Data Sheet 2019-05-30
Intel Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis 2018-05-09
Intel Quartus Prime Standard Edition Handbook Volume 3 Verification 2018-05-09
Intel SoC FPGA Embedded Development Suite User Guide 2019-05-16
LVDS SERDES Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices 2019-05-03
Low Latency 100-Gbps Ethernet IP Core User Guide 2018-01-03
Low Latency 40-Gbps Ethernet IP Core User Guide 2018-01-03
NCO IP Core: User Guide 2017-11-06
Native Loopback Accelerator Functional Unit (AFU) User Guide 2019-08-05
Networking Interface for Open Programmable Acceleration Engine: Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA 2019-08-05
OCT Intel FPGA IP User Guide 2019-07-03
PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces 2017-01-23
Reed-Solomon II IP Core User Guide 2016-05-02
Remote Update Intel FPGA IP Core Release Notes 2018-05-07
SerialLite II IP Core User Guide 2019-01-09
Tandem Motion-Power 48 V Board Reference Manual 2016-08-01
Unique Chip ID Intel FPGA IP Core Release Notes 2018-05-07
Using Intel Arria 10 SoC FPGA Early I/O Release 2018-10-11
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